08-25-2020 12:08 PM
My custom design has PCIe and I have followed the 'Custom Flow' procedure from the documentation. The only mistake I did was I dint disable the PCIe before the flash programming. The PCI link has gone down and the LED lights up only for a couple of seconds during the cold reboot. I have even tried the ideas given in this thread ( https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/Alveo-U50-DMB-1-No-device-detected-on-target/td-p/1108140 ) but it was of no use. Vivado's hardware manager too doesn't detect the card.
Any ideas as to how to reset the card without the PCIe.
P.S. xbutil and xbmgmt throw an error saying the card has not been found.
08-25-2020 02:10 PM
xbutil and xbmgmt will not be available to you if you create a custom project design instead of a design in Vitis.
Likely you have created a design that does not drive the HBM cat trip pin to the satellite controller correctly.
Here is an excerpt from another thread on how you may try to recover the card
08-25-2020 02:14 PM
I have a quick silly question.
The XDC file says that we have to drive the cat_trip pin to avoid power rail failures.
I am using the following commands :
set_property PACKAGE_PIN J18 [get_ports "HBM_CATTRIP"]
set_property IOSTANDARD LVCMOS18 [get_ports "HBM_CATTRIP"]
But when I open the synthesized design there are critical warnings that the set_property and get_ports don't return any value.
Should the QSFP28 IP be included for this to work? In my current design, I have the XDMA IP and doesn't it have the HBM settings. Not sure what I am supposed to do here
08-26-2020 09:41 AM
You need to have a top level port in your design called "HBM_CATTRIP" in order for those XDC constraints to work.
The cattrip signal should be coming from the HBM, if there is no HBM in the design, create a wire and drive it to 1'b0 and call that HBM_CATTRIP.
08-26-2020 12:30 PM
You should make changes in an RTL / Text editor. I suppose you could edit a schematic in ISE if you are familiar with that flow, but I can't help you with that. Ultimately you need this defined in the top level of your RTL designed so you can assign the wire to a port.