11-11-2019 04:03 AM
Can I get pin constraints for alveo u200 board? I need sys_reset, gt_ref_clk, init_clk and all lowspeed interface pins for qsfp0 and qsfp1.
Also I want to get official project (not sdaccel) in which I can modify qsfp registers right way due to question from next post:
Am I need to write 93 register in qsfp in Alveo u200 through i2c fpga's port ? Or does qsfp modules turned on right way automatically in alveo?
11-12-2019 09:50 AM
I have received lots of requests in the past for pinouts but I have never received a query about writing to registers on the QSFP.
Here is the way we've been solving this style of question in the past -
Use this link to download the Vivado constraint and board files for the u200
Use this link to get the QSFP up and running
Could you let me know if this works for you?
11-13-2019 03:39 AM
I've downloaded xdc file but I can't uderstand meaning of some qsfp pins in it. If I'll implement simply 100g subsystem example project from box with this xdc file without adding any pins will design work? Or am I need to add some lowspeed qsfp pins from xdc to design such as lpmode0, fs0, modskll_ls to example project?
Also I can't succeed due to your second link using block design. Automation of connections does not work good with eth subsystem and and I can't get output products. Second trouble is that I don't know alveo schematics and can't imagine how to set low speed signals properly. And I don't know role of i2c bus in setting of qsfp module parameters. Some vendors requires that.A I understood I don't need i2c in Alveo. Am I right?
11-18-2019 05:28 AM
11-18-2019 05:30 AM
11-18-2019 08:27 AM
Hi @slipknotchik ,
The low speed signals for the U200 / U250 Alveo cards are driven directly from the FPGA, so would need to be set via the Ethernet IP / QSFP requirements training requirements. These are defined in the specifications for SFF QSFP ethernet, and are referenced in User Guide 1289 (Alveo U200/U250 User Guide). Per that User Guide, these are available via I2C as well. The I2C is available for instantiation via block automation.
If you are having challenges with block automation specific to the Ethernet IP and connectivity requirements, I would recommend you review the Ethernet User Guide for the core you are targeting, as well post to the Ethernet forums, as they may have more specific advice.
Please review User Guide 1289 (Alveo U200/U250 User Guide) - as this has more information on the reference clocks and locations. These should also be selectable in block automation.
11-18-2019 10:38 AM
11-19-2019 03:56 AM
12-04-2019 09:31 AM
I'm trying to get you some more answers to your questions. I don't think I2C is the way to go, and we do not have I2C register definitions or schematics to provide.
If I'll implement simply 100g subsystem example project from box with this xdc file without adding any pins will design work?
Probably not. The example projects are not board aware and they do not inherit the board file information from the board files. You could use the XDC but you'd need to set all the IPs and clocks correctly. The best way for you to determine what the IP configuration should be would be starting with an IPI design and using those settings as a reference. There's also a matter of the XDC pin names aren't always obvious.
Or am I need to add some lowspeed qsfp pins from xdc to design such as lpmode0, fs0, modskll_ls to example project?
lpmode0 should be 0
Also I can't succeed due to your second link using block design. Automation of connections does not work good with eth subsystem and and I can't get output products.
So unfortunately, where we are at with the GT reference designs and what is required to get Ethernet IP working we don't have additional reference material. Should be coming soon and I understand your frustration. For example, there is no way to connect the LBUS interface to anything in IPI, so you'd need to use the AXI streaming interface.
I read about provided design files with examples and docs in ug1352. How can I download it?
I made a quick and ugly block diagram with a CMAC using the board flow, then I generated a wrapper for this block so that you can use it in a RTL design.
I don't know if this will work but it should get you unstuck for now.
01-24-2020 07:58 AM
sorry if i get the discussion now,
I'm delevoping 100G on VCU1525, I read your last post in particular:
"Or am I need to add some lowspeed qsfp pins from xdc to design such as lpmode0, fs0, modskll_ls to example project?
lpmode0 should be 0"
The specification you linked cites:
LPMode/TxDis is a dual-mode input signal from the host operating with active high
logic. It shall be pulled towards Vcc in the module. At power-up or after ResetL is
deasserted LPMode/TxDis behaves as LPMode. If supported, LPMode/TxDis can be
configured as TxDis using the two-wire interface except during the execution of a
reset. TxDis provides an optional fast mode, see definition in SFF-8636.
When LPMode/TxDis is configured as LPMode, the module behaves as though TxDis=0. By
using the LPMode signal and a combination of the Power_override, Power_set and
High_Power_Class_Enable software control bits (SFF-8636, Address A0h, Byte 93 bits
0,1,2), the host controls how much power a module can consume. See section 5.6 for
more details on the power supply specifications.
When LPMode/TxDis is configured as TxDis, the module behaves as though LPMode=0.
In this mode LPMode/TxDis when set to 1 or 0 disables or enables all optical
transmitters within the times specified in Table 8-2.
Now the document says LPmode have to be set to Vcc not to 0, in this case you have Tx enabled
but at the lower trasmission power (that is 1.5W).
From the specification it is not enough to set LPMode to zero if you don't set the pin to function as TxDis.
In case you set the pin as TxDis by I2C, LPMmode = 0 will enable the trasmission.
Does Xilinx set this pin like TxDis at boot time by I2C?
Just for example in the VCU1525 the schematic pulls the LPMode pin to Vcc (UG1268 v1.0)