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Contributor
Contributor
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Registered: ‎05-29-2018

CMAC compile error due to license problem

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Dear, 

I got an error related to license when generating bitfile. 
I used Vivado 2019.1 (Alveo U280).
When I used Vivado 2018.2 for VCU1525, I sucessfully got the bitfile.
Does anyone know this issue?
 
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
u_cmac_1/inst/i_cmac_usplus_1_top (<encrypted cellview>)
u_cmac_0/inst/i_cmac_usplus_0_top (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
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Xilinx Employee
Xilinx Employee
324 Views
Registered: ‎10-19-2015

Hi @toku1938 

I'm not sure if there is a benefit to tcl scripting this IP into your project. I understand there was benefit to that approach with the 1525, have you looked at the new board aware flow documented in AR71981 ?

Can you check in the GUI and verify you have a license for the CMAC? Do this by openeing Vivado in 2019.1, going to the IP Catalog and selecting the CMAC IP. When the Customization GUI opens up look in the bottom left corner for the license status. 

Here is an examplecmac license.PNG

It seems possible to me that your license could have expired between 2018.2 and 2019.1 

Regards,

M

 

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Xilinx Employee
Xilinx Employee
383 Views
Registered: ‎10-19-2015

Hi @toku1938 

How are you adding the CMAC IP into your design? 

The message might be from the fact that the CMAC IP's license was not available during synthesis. We'd want to determine how the CMAC was synthesized initially.

Regards,

M

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Contributor
Contributor
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Registered: ‎05-29-2018
I added CMAC IP like this (Basically, I did it GUI, I pasted the tcl of that.).

create_ip -name cmac_usplus -vendor xilinx.com -library ip -version 2.6 -module_name cmac_usplus_0
set_property -dict [list CONFIG.CMAC_CAUI4_MODE {1} CONFIG.NUM_LANES {4} CONFIG.GT_REF_CLK_FREQ {161.1328125} CONFIG.TX_FLOW_CONTROL {0} CONFIG.RX_FLOW_CONTROL {0} CONFIG.INCLUDE_RS_FEC {1} CONFIG.ENABLE_AXI_INTERFACE {0} CONFIG.INCLUDE_STATISTICS_COUNTERS {0} CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y7} CONFIG.GT_GROUP_SELECT {X0Y40~X0Y43} CONFIG.LANE1_GT_LOC {X0Y40} CONFIG.LANE2_GT_LOC {X0Y41} CONFIG.LANE3_GT_LOC {X0Y42} CONFIG.LANE4_GT_LOC {X0Y43} CONFIG.LANE5_GT_LOC {NA} CONFIG.LANE6_GT_LOC {NA} CONFIG.LANE7_GT_LOC {NA} CONFIG.LANE8_GT_LOC {NA} CONFIG.LANE9_GT_LOC {NA} CONFIG.LANE10_GT_LOC {NA} CONFIG.RX_GT_BUFFER {1} CONFIG.GT_RX_BUFFER_BYPASS {0}] [get_ips cmac_usplus_0]
generate_target {instantiation_template} [get_files project_1/project_1.srcs/sources_1/ip/cmac_usplus_0/cmac_usplus_0.xci]
update_compile_order -fileset sources_1
generate_target all [get_files project_1/project_1.srcs/sources_1/ip/cmac_usplus_0/cmac_usplus_0.xci]
catch { config_ip_cache -export [get_ips -all cmac_usplus_0] }
export_ip_user_files -of_objects [get_files project_1/project_1.srcs/sources_1/ip/cmac_usplus_0/cmac_usplus_0.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] project_1/project_1.srcs/sources_1/ip/cmac_usplus_0/cmac_usplus_0.xci]
launch_runs -jobs 4 cmac_usplus_0_synth_1
export_simulation -of_objects [get_files project_1/project_1.srcs/sources_1/ip/cmac_usplus_0/cmac_usplus_0.xci] -directory project_1/project_1.ip_user_files/sim_scripts -ip_user_files_dir project_1/project_1.ip_user_files -ipstatic_source_dir project_1/project_1.ip_user_files/ipstatic -lib_map_path [list {modelsim=project_1/project_1.cache/compile_simlib/modelsim} {questa=project_1/project_1.cache/compile_simlib/questa} {ies=project_1/project_1.cache/compile_simlib/ies} {xcelium=project_1/project_1.cache/compile_simlib/xcelium} {vcs=project_1/project_1.cache/compile_simlib/vcs} {riviera=project_1/project_1.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet
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Xilinx Employee
Xilinx Employee
325 Views
Registered: ‎10-19-2015

Hi @toku1938 

I'm not sure if there is a benefit to tcl scripting this IP into your project. I understand there was benefit to that approach with the 1525, have you looked at the new board aware flow documented in AR71981 ?

Can you check in the GUI and verify you have a license for the CMAC? Do this by openeing Vivado in 2019.1, going to the IP Catalog and selecting the CMAC IP. When the Customization GUI opens up look in the bottom left corner for the license status. 

Here is an examplecmac license.PNG

It seems possible to me that your license could have expired between 2018.2 and 2019.1 

Regards,

M

 

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