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Participant
Participant
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Registered: ‎01-27-2019

Stuck when loading Binary file using ALVEO u280 es1

Hi all:

I meet a problem when loading binary file on board. I have used SDAccel to generate the executeable and binary file successfully. However, when I try to load these two files on the board, it will always stuck here.problem.pngI have to stop uploading, when I open the dmesg, I can see the information below:Screenshot from 2019-09-03 10-48-04.png

I have never met such a problem when uploading the binary file, can someone help?

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Participant
Participant
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Registered: ‎01-27-2019

Can anyone give me some suggestions for solving the problems?

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Xilinx Employee
Xilinx Employee
547 Views
Registered: ‎10-19-2015

Hi @rookicoe 

I'd like to know a little more about the system. 

What commands or tools are you using to program the card? 

Which XRT? 

Which Shell? 

Please send me the output of 

$xbutil query 

 

before and after you try programming the xclbin onto the board. 

 

Can you run xbutil validate successfully? 

 

$xbutil validate

Regards,

 

M

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Participant
Participant
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Registered: ‎01-27-2019

Hi @mcertosi :

Thanks for your reply,

1. I type ./Executable.exe binary_container_1.xclbin

2. XRT version:xrt_201830.2.1.1748_18.04-xrt

3. Shell Version: xilinx-u280-es1-xdma-201830.1-2476212_18.04

Xbutil query output before mapping FPGA:

INFO: Found total 1 card(s), 1 are usable
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XRT
Version: 2.1.1748
Git Hash: d38a68808897417b90fcdd7d35f54fc89b2de449
Git Branch: 2018.3
Build Date: 2019-03-08 15:06:20
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DSA FPGA IDCode
xilinx_u280-es1_xdma_201830_1 xcu280-fsvh2892-2L-e-es1 0x4b7d093
Vendor Device SubDevice SubVendor
0x10ee 0x5008 0xe 0x10ee
DDR size DDR count Clock0 Clock1
34359738368 2 300 500
PCIe DMA chan(bidir) MIG Calibrated P2P Enabled
GEN 3x16 2 true false
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Temperature(C)
PCB TOP FRONT PCB TOP REAR PCB BTM FRONT
35 34 36
FPGA TEMP TCRIT Temp FAN Speed(RPM)
41 35 1102
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Electrical(mV|mA)
12V PEX 12V AUX 12V PEX Current 12V AUX Current
12119 12191 1177 817
3V3 PEX 3V3 AUX DDR VPP BOTTOM DDR VPP TOP
3287 3416 2500 2500
SYS 5V5 1V2 TOP 1V8 TOP 0V85
5467 1205 1805 861
MGT 0V9 12V SW MGT VTT
902 12151 1210
VCCINT VOL VCCINT CURR DNA
850 7398
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Board Power
24 W
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Firewall Last Error Status
Level 0 : 0x0(GOOD)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Memory Status
Tag Type Temp(C) Size Mem Usage BO count
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DMA Transfer Metrics
Chan[0].h2c: 0 Byte
Chan[0].c2h: 0 Byte
Chan[1].h2c: 0 Byte
Chan[1].c2h: 0 Byte
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Xclbin UUID
00000000-0000-0000-0000-000000000000
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Compute Unit Status
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
INFO: xbutil query succeeded.

 

 

 

Xbutil query output after mapping FPGA(Because it will stuck so I just interrupt the mapping by ctrl+C):

INFO: Found total 1 card(s), 1 are usable
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XRT
Version: 2.1.1748
Git Hash: d38a68808897417b90fcdd7d35f54fc89b2de449
Git Branch: 2018.3
Build Date: 2019-03-08 15:06:20
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DSA FPGA IDCode
xilinx_u280-es1_xdma_201830_1 xcu280-fsvh2892-2L-e-es1 0x4b7d093
Vendor Device SubDevice SubVendor
0x10ee 0x5008 0xe 0x10ee
DDR size DDR count Clock0 Clock1
34359738368 2 250 500
PCIe DMA chan(bidir) MIG Calibrated P2P Enabled
GEN 3x16 2 true false
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Temperature(C)
PCB TOP FRONT PCB TOP REAR PCB BTM FRONT
37 34 36
FPGA TEMP TCRIT Temp FAN Speed(RPM)
42 35 1102
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Electrical(mV|mA)
12V PEX 12V AUX 12V PEX Current 12V AUX Current
12103 12173 1380 1192
3V3 PEX 3V3 AUX DDR VPP BOTTOM DDR VPP TOP
3308 3416 2500 2500
SYS 5V5 1V2 TOP 1V8 TOP 0V85
5476 1207 1817 862
MGT 0V9 12V SW MGT VTT
902 12105 1212
VCCINT VOL VCCINT CURR DNA
851 9012
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Board Power
31 W
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Firewall Last Error Status
Level 0 : 0x0(GOOD)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Memory Status
Tag Type Temp(C) Size Mem Usage BO count
[ 0] HBM[0] MEM_DDR4 36 256 MB 0 Byte 0
[ 1] HBM[1] MEM_DDR4 36 256 MB 0 Byte 0
[ 2] HBM[2] **UNUSED** 0 0 Byte 0 Byte 0
[ 3] HBM[3] **UNUSED** 0 0 Byte 0 Byte 0
[ 4] HBM[4] **UNUSED** N/A 0 Byte 0 Byte 0
[ 5] HBM[5] **UNUSED** N/A 0 Byte 0 Byte 0
[ 6] HBM[6] **UNUSED** N/A 0 Byte 0 Byte 0
[ 7] HBM[7] **UNUSED** N/A 0 Byte 0 Byte 0
[ 8] HBM[8] **UNUSED** N/A 0 Byte 0 Byte 0
[ 9] HBM[9] **UNUSED** N/A 0 Byte 0 Byte 0
[10] HBM[10] **UNUSED** N/A 0 Byte 0 Byte 0
[11] HBM[11] **UNUSED** N/A 0 Byte 0 Byte 0
[12] HBM[12] **UNUSED** N/A 0 Byte 0 Byte 0
[13] HBM[13] **UNUSED** N/A 0 Byte 0 Byte 0
[14] HBM[14] **UNUSED** N/A 0 Byte 0 Byte 0
[15] HBM[15] **UNUSED** N/A 0 Byte 0 Byte 0
[16] HBM[16] **UNUSED** N/A 0 Byte 0 Byte 0
[17] HBM[17] **UNUSED** N/A 0 Byte 160 GB 0
[18] HBM[18] **UNUSED** N/A 0 Byte 0 Byte 2
[19] HBM[19] **UNUSED** N/A 0 Byte 0 Byte 40
[20] HBM[20] **UNUSED** N/A 0 Byte 0 Byte 0
[21] HBM[21] **UNUSED** N/A 0 Byte 0 Byte 0
[22] HBM[22] **UNUSED** N/A 0 Byte 0 Byte 0
[23] HBM[23] **UNUSED** N/A 0 Byte 0 Byte 0
[24] HBM[24] **UNUSED** N/A 0 Byte 0 Byte 0
[25] HBM[25] **UNUSED** N/A 0 Byte 0 Byte 0
[26] HBM[26] **UNUSED** N/A 0 Byte 127 TB 0
[27] HBM[27] **UNUSED** N/A 0 Byte 10447 PB 0
[28] HBM[28] **UNUSED** N/A 0 Byte 85 TB 0
[29] HBM[29] **UNUSED** N/A 0 Byte 127 TB 0
[30] HBM[30] **UNUSED** N/A 0 Byte 127 TB 0
[31] HBM[31] **UNUSED** N/A 0 Byte 4095 MB 0
[32] DDR[0] MEM_DRAM N/A 16 GB 127 TB 0
[33] DDR[1] MEM_DRAM N/A 16 GB 127 TB 0
[34] PLRAM[0] **UNUSED** N/A 128 KB 127 TB 0
[35] PLRAM[1] **UNUSED** N/A 128 KB 85 TB 0
[36] PLRAM[2] **UNUSED** N/A 128 KB 127 TB 2015460816
[37] PLRAM[3] **UNUSED** N/A 128 KB 127 TB 32653
[38] PLRAM[4] **UNUSED** N/A 128 KB 127 TB 261139456
[39] PLRAM[5] **UNUSED** N/A 128 KB 85 TB 2738621899
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DMA Transfer Metrics
Chan[0].h2c: 4576 MB
Chan[0].c2h: 1344 MB
Chan[1].h2c: 4320 MB
Chan[1].c2h: 1088 MB
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Xclbin UUID
0f4f3a3f-90d8-4a14-ab0d-6be8ea5381b4
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Compute Unit Status
CU[ 0]: bandwidth1:kernel_1 @0x1800000 (IDLE)
CU[ 1]: bandwidth2:kernel_2 @0x1810000 (IDLE)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
INFO: xbutil query succeeded.

 

And I can successfully run xbutil validate

 

Regards

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Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎10-19-2015

Hi @rookicoe 

Can you load the XCLBIN with xbutil? 

xbutil program -p ./binary_container_1.xclbin

If that doesn't work, then I'd think there is something wrong with the xclbin, so we would want to look at the logs from the _x directory wherever the xclbin was built. 

If xbutil program works, then we want to debug the host code. Can you determine exactly which call is failing? 

Could you update to the latest xrt from Xilinx.com and test again? 

https://www.xilinx.com/products/boards-and-kits/alveo/u280.html#gettingStarted

Regards,

M

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Participant
Participant
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Registered: ‎01-27-2019

Hi @mcertosi :

Sincerely thanks for your reply, I believe the problem is caused by the xclbin, because when i use

xbutil program -p ./binary_container_1.xclbin

 It still cannot work and will stuck again.

I have reviewed the log file, but there are several critical warnings, after comparing with the test log file(belong to the test project which can be successfully mapping on FPGA), I find some critical warnings which are new.

First one:

CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] bd_5dca_interconnect1_1_0: WUSER_WIDTH (1) of S00_AXI must be integer number of bits per byte of WDATA (64).
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] bd_5dca_interconnect2_2_0: WUSER_WIDTH (1) of S00_AXI must be integer number of bits per byte of WDATA (64).
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] bd_5dca_interconnect3_3_0: WUSER_WIDTH (1) of S00_AXI must be integer number of bits per byte of WDATA (64).
CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] bd_5dca_interconnect4_4_0: WUSER_WIDTH (1) of S00_AXI must be integer number of bits per byte of WDATA (64).

 

Second one:

CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

 

I am not sure whether the problem is caused by these two critical warnings, I also upload my log file. If you have time, would you mind help me to check this log file? Thx!

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2015

Hi @rookicoe 

When a design fails to meet timing there is no way to guarantee anything will work correctly in your xclbin. 

Did you design this binary container yourself? 

Have you verified its functionality using hardware emulation? 

Can you send me the output of 

$xclbinutil -i ./binary_container.xclbin --info >> xclbin_info.log

as well as the vivado.jou log from the _x directory? 

The critical warnings you've cited seem relevant. 

What's the difference between the project that works and this one? 

Regards,

M

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Participant
Participant
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Registered: ‎01-27-2019

Hi @mcertosi :

Thanks for your kind help, I have uploaded the xclbin_info.log and vivado.jou is as following:

 

#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Sep 6 15:46:35 2019
# Process ID: 18661
# Current directory: /home/jiale/DebugforKernelLoading/Firesimwithoutwuser/Firesimwithouwuser/System/binary_container_1/link/vivado
# Command line: vivado -mode batch -notrace -source /home/jiale/DebugforKernelLoading/Firesimwithoutwuser/Firesimwithouwuser/System/binary_container_1/link/vivado/ipirun.tcl -messageDb /home/jiale/DebugforKernelLoading/Firesimwithoutwuser/Firesimwithouwuser/System/binary_container_1/link/vivado/vivado.pb
# Log file: /home/jiale/DebugforKernelLoading/Firesimwithoutwuser/Firesimwithouwuser/System/binary_container_1/link/vivado/vivado.log
# Journal file: /home/jiale/DebugforKernelLoading/Firesimwithoutwuser/Firesimwithouwuser/System/binary_container_1/link/vivado/vivado.jou
#-----------------------------------------------------------
source /home/jiale/DebugforKernelLoading/Firesimwithoutwuser/Firesimwithouwuser/System/binary_container_1/link/vivado/ipirun.tcl -notrace

 

 

This binary_container_1 is not designed by myself and I rememeber that the last time I use hardware emulation, it gives the result below:

INFO: Selected platform 0 from Xilinx
INFO: Found 1 devices
CL_DEVICE_NAME xilinx_u280-es1_xdma_201830_1
Selected xilinx_u280-es1_xdma_201830_1 as the target device
INFO: loading xclbin binary_container_1.xclbin
INFO: [SDx-EM 01] Hardware emulation runs simulation underneath. Using a large data set will result in long simulation times. It is recommended that a small dataset is used for faster execution. This flow does not use cycle accurate models and hence the performance data generated is approximate.
INFO: [SDx-EM 22] [Wall clock time: 15:28, Emulation time: 0.854853 ms] Data transfer between kernel(s) and global memory(s)
Debug13_1:m00_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB
Debug13_1:m01_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB
Debug13_1:m02_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB
Debug13_1:m03_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB

INFO: [SDx-EM 22] [Wall clock time: 15:33, Emulation time: 1.70999 ms] Data transfer between kernel(s) and global memory(s)
Debug13_1:m00_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB
Debug13_1:m01_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB
Debug13_1:m02_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB
Debug13_1:m03_axi-HBM[0] RD = 0.000 KB WR = 0.000 KB

The difference between the project that works and this one is their RTL Kernels.

What's more, this design now doesn't have any timing constrain. I originally try to add some timing constrains to this project, but it will emerge some mistakes in the process of system emulation when using SDAccel, says that hold violation. However, it can pass the implementation in xilinx kernel wizard.

I will try to look up the source file of this design.

 

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