12-30-2019 09:32 AM
We bought a U200 board and cannot use XRT framework. We need to communicate with the U200 board over PCIe bridge.
We are using Vivado 2019.2. I tried to develop a very simple application (basically DMA subsystem for PCIe +DDR4 SDRAM ((c0)), but it fails in DRC pin planning, complaining that the pci_express_x8_txp use DEFAULT as IOSTANDARD but it requires a user assigned specific value. THe xdc file alveo-u200-xdc.xdc which can be dowloaded does not help me. Which value should I use?
... Or has anyone a working basic example
Thanks in advance for your help
01-02-2020 08:50 AM
XRT and the U200 work without the need of Vivado or an XDC file.
You have referenced two separate flows in your original problem statement, one using XRT and one using XDC.
XRT is not expected to work with a custom design where a user starts in Vivado and requires an XDC file.
XRT is expected to work with an acceleration application created in either SDAccel or Vitis. If you're interested in an example of how to program the accelerator card or write a kernel follow this link here: https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/
Could you tell me more about what you are interested in doing so I can provide more resources?
01-02-2020 09:05 AM
01-02-2020 09:15 AM
Correct, looks like the XDC file is incomplete. Are you designing in IPI? If so, you could use these board files which do seem to be complete. https://github.com/Xilinx/XilinxBoardStore/tree/master/boards/Xilinx
Only other option is to generate an acceleration design using Vitis, then opening up the underlying Vivado project and generating the XDC file from there. Each Vitis project has an _x directory, so open that and navigate to the .xpr. Open the implemented design and use write_xdc tcl command. This might not be straight forwards as the port names might be different than expected.
You could use the Kernel Global Bandwidth project as a reference. https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/
01-03-2020 04:42 AM