cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
333 Views
Registered: ‎03-26-2018

U200 pci_express IOSTANDARD

Hi,

We bought a U200 board and cannot use XRT framework. We need to communicate with the U200 board over PCIe bridge.

We are using Vivado 2019.2. I tried to develop a very simple application (basically DMA subsystem for PCIe +DDR4 SDRAM ((c0)),  but it fails in DRC pin planning, complaining that the pci_express_x8_txp use DEFAULT as IOSTANDARD but it requires a user assigned specific value. THe xdc file alveo-u200-xdc.xdc which can be dowloaded does not help me. Which value should I use?

... Or has anyone a working basic example

Thanks in advance for your help

JP

Tags (2)
0 Kudos
5 Replies
Highlighted
Observer
Observer
309 Views
Registered: ‎03-26-2018

Re: U200 pci_express IOSTANDARD

This is related to the issue discussed in "U200 and U250 constraint files broken"
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
235 Views
Registered: ‎10-19-2015

Re: U200 pci_express IOSTANDARD

Hi @jpbb 

XRT and the U200 work without the need of Vivado or an XDC file.

You have referenced two separate flows in your original problem statement, one using XRT and one using XDC. 

XRT is not expected to work with a custom design where a user starts in Vivado and requires an XDC file. 

XRT is expected to work with an acceleration application created in either SDAccel or Vitis. If you're interested in an example of how to program the accelerator card or write a kernel follow this link here: https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/

Could you tell me more about what you are interested in doing so I can provide more resources? 

Regards,

M

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
230 Views
Registered: ‎03-26-2018

Re: U200 pci_express IOSTANDARD

Hi M!
We do not want to use the board as an HW accelerator. In our application, we configure the logic part at start-up (memory/registers) and then go into a run mode, where the PL generates a stream of data which will ultimately be sent over an auroa link (on QSFP). I realize that I cannot use VITIS/XRT framework and I will have to use only Vivado and adapt PCI DMA driver, I guess.

The xdc file is imcomplete (I am not the only person to complain.

The best information would be to get an simple example which partly populates one of the 4 memory banks or other registers from a Linux application over PCIe, .... but the traditional way

Any help will be appreciated!
Cheers
JP




0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
224 Views
Registered: ‎10-19-2015

Re: U200 pci_express IOSTANDARD

Hi @jpbb 

Correct, looks like the XDC file is incomplete. Are you designing in IPI? If so, you could use these board files which do seem to be complete. https://github.com/Xilinx/XilinxBoardStore/tree/master/boards/Xilinx 

Only other option is to generate an acceleration design using Vitis, then opening up the underlying Vivado project and generating the XDC file from there. Each Vitis project has an _x directory, so open that and navigate to the .xpr. Open the implemented design and use write_xdc tcl command. This might not be straight forwards as the port names might be different than expected. 

You could use the Kernel Global Bandwidth project as a reference. https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/ 

Regards,

M

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
164 Views
Registered: ‎03-26-2018

Re: U200 pci_express IOSTANDARD

Hi M,
I think the easiest way would be to let Xilinx update all constraint files for the Alveo family(U50,..., u280).
I designed my project with Vivado 2019.2 and use the u200 board. I guess it is pointing to the right .../Vivado/2019.2/data/boards/board_files/au200/v1.3/..
I tried to fix the alveo-u200-xdc.xdc (or at least the port I used). There are some commands like:
set_property IOSTARDARD [get_port PEX_TX15_N];
Which IOSTANDARD does it mean there?
I do not want to do reverse engineering by introspecting the file generated by Vitis.

I saw that bob.wittosh@hellastorm.com posted a similar issue with u280. He managed to fix it after long efforts.

I would wish to get a minimal application, whose project is built in Vivado only for u200. Communication with the board is done from a C/C++ application using Xilinx DAM linux driver for instance. Do anyone develop that earlier?
Thanks again for all help you can give me
cheers
JP






0 Kudos