10-26-2019 06:13 PM
I just acquired an alveo u250 board and I would like to port an existing vcu118 design to it. This design has pcie, ddr and fiber interfaces on it already and I'd like to use the full resources of the chip instead of letting some of it go to the static portion for SD support.
I understand that this is not fully supported so I'm trying to understand if there is any hard stops to prevent this. Is it possible to just use the board as if it's a regular dev kit ala vcu118 without needing or using any of the SD support.
10-27-2019 05:48 AM
You can create a new vivado project and select U250 and just at your hardware/IPs. You will have access to all resources.
After that you can program the card SPI NOR flash via management interface.
You can find the instruction(UG1289) and also XDC files here: https://www.xilinx.com/products/boards-and-kits/alveo/u250.html#documentation
12-28-2019 10:49 AM
Do you know which clocks are active without taking any action? I implemented a tiny, trivial counter design to blink the 3 leds which implemented and programmed but can't observe any blinking.
01-02-2020 08:58 AM
Clocks should be up and running without action. There is no way for users to control the frequency of the oscillators on the card.
The LEDs might not be able to be driven from the user logic. There might be an interaction with the satellite controller that is preventing it. Had you ever loaded a shell onto the U250?
BTW, you don't lose any logic to the static shell that is not being actively used by the acceleration environment. The shells are dynamic, meaning only logic that is active in your design will be synthesized and used in the shell. This is different from other shell based acceleration platforms.
01-02-2020 09:59 AM
Thanks for the feedback. I have just received the schematics and will check the LED connectivity.
In the mean time, can you point me to a "blank" shell which doesn't use any (much) resources ? It would be interesting to try.
01-02-2020 10:06 AM
Shell building blocks are synthesized during the generation of the .XCLBIN file. The specific building blocks are generated are defined in the MakeFile for your build. The XOCC or V++ tags will connect your kernel to available shell logic. Any shell logic that is not specifically used with a compiler/link tag will not be generated. This is where the logic saving happens.
So to see an example of this, you could use the kernel_global_bandwidth example project. One run you should synthesize 1 DDR bank, in another run you should synthesize > 1 DDR banks. You'll see in the single DDR design that the other DDR banks are not used and those logic resources are free to be used with your acceleration kernel.
Does that help?