cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
g_sai
Visitor
Visitor
350 Views
Registered: ‎04-13-2021

synth ERROR vpl failed for u50 while building xclbin

Jump to solution

Sir,

I am facing error while generating xclbin file accelerated algorithmic trading design using U50. Can you please help me in solving the error. I am attaching log file and screenshot

Thanks in advance

Screenshot from 2021-04-13 22-14-15.png
0 Kudos
1 Solution

Accepted Solutions
emeryw
Xilinx Employee
Xilinx Employee
136 Views
Registered: ‎12-06-2019

Hi @g_sai ,

The Vitis documentation comprehensively covers this and many other topics: https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitiscommandcompiler.html#pbx1568640588680__section_nlp_yhv_dnb

To increase the amount of free physical memory, reduce the amount of memory currently in use (close applications, etc.), or add more physical memory to the machine.

Best,
-Emery
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

6 Replies
emeryw
Xilinx Employee
Xilinx Employee
270 Views
Registered: ‎12-06-2019

Hi @g_sai ,

I downloaded this example and followed the instructions in UG1067. Using 2020.2 of the tools and XRT, the project built successfully for the Alveo U50. Unfortunately, the attached log file does not give a good indication of what caused your build to fail. I compared it with the log file produced by my system; besides file path differences the commands issued were the same. Could you check the build/_x/ folder for any additional log files that may give a better idea of what happened? Some of the directories inside of the hw/ folder may contain Vivado projects, which can be opened to review any errors that Vivado reports.

Have you built any other Vitis-based example projects successfully with your system? Are you using the latest download of the Accelerated Algorithmic Trading project?

Best,
-Emery
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

0 Kudos
g_sai
Visitor
Visitor
238 Views
Registered: ‎04-13-2021

hi @emeryw 

I have found some log files in the _x folder. I am attaching it here. I have downloaded the latest Accelerated Algorithmic Trading files on 8th April 2021.

Can you please some solution to my problem.

Thanks in Advance

 

0 Kudos
emeryw
Xilinx Employee
Xilinx Employee
184 Views
Registered: ‎12-06-2019

Hi @g_sai ,

A couple of thoughts here. I diffed your logs against my build directory, which didn't tell us much more than we already knew; the bottom of link.steps.log reports the following:

-----------------------
  current step: vpl.synth
   -----------------------
   VPL internal step: launch_runs my_rm_synth_1 -jobs 4  
   File: vpl.tcl:492
   timestamp: 15 April 2021 19:16:10
   VPL internal step status: fail

To get more info, check the log for the synth run mentioned above. It should be sitting in _x/logs/link/syn/. I also noted, but may not be contributing to the issue at hand, that your system launches more jobs, but appears to have very little physical memory resources available. As more jobs requires more memory and CPU resources, it may be a good idea to reduce the number of jobs or increase the amount of free physical memory.

Best,
-Emery
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------


g_sai
Visitor
Visitor
157 Views
Registered: ‎04-13-2021

hi @emeryw 

Thanks for the idea. Can you help me how to reduce the number of jobs or increase the amount of free physical memory.

Thanks in advance

0 Kudos
emeryw
Xilinx Employee
Xilinx Employee
137 Views
Registered: ‎12-06-2019

Hi @g_sai ,

The Vitis documentation comprehensively covers this and many other topics: https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitiscommandcompiler.html#pbx1568640588680__section_nlp_yhv_dnb

To increase the amount of free physical memory, reduce the amount of memory currently in use (close applications, etc.), or add more physical memory to the machine.

Best,
-Emery
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

g_sai
Visitor
Visitor
58 Views
Registered: ‎04-13-2021

hi @emeryw 

Thanks for the help

0 Kudos