According to latest ug1301,
xbutil validate demo has been support the HBM test (DDR&DMA) on U280 ES1 card,
Could you help share the performance or the test detailed report to us, we may
evaluate the HBM accordingly?
A Xilinx engineer has created a simple OpenCL test for demonstrating maximum bandwidth of HBM usage through SDAccel flow. You may be able to leverage this design.