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Registered: ‎04-02-2019

u280 clocks.

Hi,

I am looking for a document which describe all the clocks in u280 with their frequencies so that i can correctly constraint my design.

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set_property PACKAGE_PIN T43 [get_ports "MGT_SI570_CLOCK0_C_N"] ;# Bank 134 - MGTREFCLK0N_134
set_property PACKAGE_PIN T42 [get_ports "MGT_SI570_CLOCK0_C_P"] ;# Bank 134 - MGTREFCLK0P_134
set_property PACKAGE_PIN R41 [get_ports "QSFP0_CLOCK_N"] ;# Bank 134 - MGTREFCLK1N_134
set_property PACKAGE_PIN R40 [get_ports "QSFP0_CLOCK_P"] ;# Bank 134 - MGTREFCLK1P_134
set_property PACKAGE_PIN P43 [get_ports "MGT_SI570_CLOCK1_C_N"] ;# Bank 135 - MGTREFCLK0N_135
set_property PACKAGE_PIN P42 [get_ports "MGT_SI570_CLOCK1_C_P"] ;# Bank 135 - MGTREFCLK0P_135
set_property PACKAGE_PIN M43 [get_ports "QSFP1_CLOCK_N"] ;# Bank 135 - MGTREFCLK1N_135
set_property PACKAGE_PIN M42 [get_ports "QSFP1_CLOCK_P"] ;# Bank 135 - MGTREFCLK1P_135
set_property PACKAGE_PIN AR14 [get_ports "PCIE_CLK1_N"] ;# Bank 225 - MGTREFCLK0N_225
set_property PACKAGE_PIN AR15 [get_ports "PCIE_CLK1_P"] ;# Bank 225 - MGTREFCLK0P_225
set_property PACKAGE_PIN AP12 [get_ports "SYSCLK5_N"] ;# Bank 225 - MGTREFCLK1N_225
set_property PACKAGE_PIN AP13 [get_ports "SYSCLK5_P"] ;# Bank 225 - MGTREFCLK1P_225
set_property PACKAGE_PIN AL14 [get_ports "PCIE_CLK0_N"] ;# Bank 227 - MGTREFCLK0N_227
set_property PACKAGE_PIN AL15 [get_ports "PCIE_CLK0_P"] ;# Bank 227 - MGTREFCLK0P_227
set_property PACKAGE_PIN AK12 [get_ports "SYSCLK2_N"] ;# Bank 227 - MGTREFCLK1N_227
set_property PACKAGE_PIN AK13 [get_ports "SYSCLK2_P"] ;# Bank 227 - MGTREFCLK1P_227
set_property PACKAGE_PIN F30 [get_ports "USER_SI570_CLOCK_N"] ;# Bank 75 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_75
set_property IOSTANDARD LVCMOSxx [get_ports "USER_SI570_CLOCK_N"] ;# Bank 75 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_75
set_property PACKAGE_PIN G30 [get_ports "USER_SI570_CLOCK_P"] ;# Bank 75 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_75
set_property IOSTANDARD LVCMOSxx [get_ports "USER_SI570_CLOCK_P"] ;# Bank 75 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_75
set_property PACKAGE_PIN F31 [get_ports "SYSCLK3_N"] ;# Bank 75 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_75
set_property IOSTANDARD LVCMOSxx [get_ports "SYSCLK3_N"] ;# Bank 75 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_75
set_property PACKAGE_PIN G31 [get_ports "SYSCLK3_P"] ;# Bank 75 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_75
set_property IOSTANDARD LVCMOSxx [get_ports "SYSCLK3_P"] ;# Bank 75 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_75
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thanks and regards,

Ishtiyaque

i.shaikh@tcs.com

 

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Xilinx Employee
Xilinx Employee
52 Views
Registered: ‎12-10-2013

Re: u280 clocks.

Hi i.shaikh@tcs.com 

An upddated XDC has been posted on the Alveo Product Page for U280.  Please download that file and review contents.  I believe it will provide the information you are looking for.

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