05-03-2008 10:54 AM
I found that this question has been asked in the past, but didn't find an answer to it, so I will try once more.
Is there a way to observe internal signals (signals other than input/output ports. signals that are only visible inside entities) when running a behavioral simulation of a VHDL code? I vaguely remember being able to drag and drop or just add to the waveform when I was using ISE webpack 9.0 or 9.1 but with 10.1 there seems to be no way to do that. I know I can do that if I use Modelsim, but I prefer using ISIM.
Thanks in advance.
05-04-2008 10:47 AM
Anything other than a variable can be viewed in ISim. Variables are tricky as they are very dynamic. Within each scope they have a different value and so it makes it very hard to be able to track it down. If you have signals you can view this. Make sure you are on the correct scope and then look in the sim objects window. In there you can see all signals. If you want, there is also a drop down box where you can select internal signals.
Hope This Helps
12-01-2008 03:26 AM
Is it also possible to access internal signals from testbench code ?
For debugging, it would be really nice to have something like:
assert (my_component.subcomponent.subsubcomponent.bus = X"abcd")
04-09-2011 09:01 PM
the same problem...just don't know how to check the internal signal in isim m8.1d which is associated with ise 12.4...anyone can tell me? all the signal appeared in the simulation objects window are just the input and output for the VHDL code , but not the internal signal ....i can just add internal signal in 10.1 version...but 12.4 seems no way to do it
02-02-2012 09:25 AM
Here is one solution I used recently. In the test bench file, at the beginning, declare a package with the signals you want to see.
use ieee.std_logic_1164.all; -- make some internal signals visible to test benches
package testbench_view_package is
signal TB_SIG_I_WANT_TO_SEE : std_logic;
-- add more signals
end package testbench_view_package;
Now the test bench can reference this as the name above.
Then in the module you want to test (aka UUT) add some code that transfers the internal signals to the new signal names.
-- For simulation make some internal signals visible to the test bench so it can verify operation
TB_VISIBILITY : if SIM_ENB = TRUE generate
-- more signals to be made visible
end generate TB_VISIBILITY;
I'm using a boolean variable SIM_ENB to control whether this is generated or not. In my design SIM_ENB is in another package with other defined constants, data types and any procedures/functions I want as globally usable. It could also be a generic passed in from the test bench.
If anyone has some better suggestions please post for us all to see.
03-14-2013 03:23 PM
I am using ISim 14.1, and I'm also trying to view internal signals. I added them in the testbench file in the form: signal abc: std_logic := '0'. They DO APPEAR in the waveform, but they never toggle. I know they are working, because I inserted them into a ChipScope cdc file and observed them. I also added more I/O signals that get a copy of the internal signal. Is there an option in ISim that I'm overlooking?