cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
rikraf
Explorer
Explorer
8,600 Views
Registered: ‎01-15-2008

Post-PAR sim does not match Post-MAP sim

Jump to solution

I have a Verilog module involving a couple of CoreGen-generated multipliers and an implied adder.  I successfully did a post-MAP sim (using ModelSim XE 6.2c), but when doing a post-PAR sim, the output is always zero.  No error messages were generated in PAR.  Any ideas?

Thanks,

Rick

0 Kudos
1 Solution

Accepted Solutions
rikraf
Explorer
Explorer
9,309 Views
Registered: ‎01-15-2008

Yes, thank you, that is what is happening, it is a timing problem.  This did not occur to me, because the PAR Timing report seemed to say that the max delay was less than 3ns, but when I slowed down the clock I found delays of 7ns.  Obviously, I'm missing something in my understanding of the tools.  I had not placed any timing constraints on the design yet, but I guess that's bad practice.  But I still don't understand the PAR timing report.  Further words of wisdom appreciated.

 

Thanks to both of you.

 

Rick

View solution in original post

0 Kudos
3 Replies
sbroderick
Visitor
Visitor
8,599 Views
Registered: ‎06-26-2008
Is it possible that one of the Core's changed? Try making mini projects for simulating and see if you can narrow it down?  Another thought is that as you approach the real-world behavior, the simulated component might need to be reset or used slightly differently. Also, try lowering the clock speed? I can't recall if/when propogation delay is considered.
0 Kudos
quiksuuver
Observer
Observer
8,577 Views
Registered: ‎08-03-2007
Only difference between post-par and post-MAP simulation should be timing.  Post-MAP simulation only take component delays into account while post-PAR simultion takes component and routing delays.  Likely you have some timing issues in your design.  Is the design properly constrained, if not, missed timing won't be caught by the tools.
0 Kudos
rikraf
Explorer
Explorer
9,310 Views
Registered: ‎01-15-2008

Yes, thank you, that is what is happening, it is a timing problem.  This did not occur to me, because the PAR Timing report seemed to say that the max delay was less than 3ns, but when I slowed down the clock I found delays of 7ns.  Obviously, I'm missing something in my understanding of the tools.  I had not placed any timing constraints on the design yet, but I guess that's bad practice.  But I still don't understand the PAR timing report.  Further words of wisdom appreciated.

 

Thanks to both of you.

 

Rick

View solution in original post

0 Kudos