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Visitor
Posts: 4
Registered: ‎09-23-2007

Synthesis Help

Hi,

i'm using ISE 9.2i and Vertex 5. I'm Implementing a multiple squaring algorithms in ISE and wish to compare their performance with each other. Here is what i get when i synthesize on of the algorithms:

"Minimum period: 4.083ns (Maximum Frequency: 244.912MHz)
Minimum input arrival time before clock: 3.180ns
Maximum output required time after clock: 2.570ns
Maximum combinational path delay: No path found"

the problem is with the "Maximum combinational path delay: No path found".

my questions are:
Is this normal, or is there something wrong that needs to be corrected?
what exactly does "Minimum period" measure, (i.e. can i use it to set the device clock frequancy), and can i use it as a performance measure?
what exactly does "Maximum pin delay" measure, and can i use it as a performance measure?

can someone please reply asap, i need this for my master's thesis.

Thanks in advance...

p.s.: if you need the code for the algorithm, i'll be happy to provide it, but please help me :).

Regards,
Saed Swedan




Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Synthesis Help

the problem is with the "Maximum combinational path delay: No path found".

my questions are:
Is this normal, or is there something wrong that needs to be corrected?

This is normal if there is no path from a top-level input to a top-level output that is not clocked.  I assume your design is fully pipelined, thus no combinatorial paths from input to output?

what exactly does "Minimum period" measure, (i.e. can i use it to set the device clock frequancy), and can i use it as a performance measure?

"Minimum period" after synthesis is an estimate of the clock period for signals inside the design.  Thus you can invert this to get a feel for maximum clock frequency.  This is not a hard actual number, as you can only see the true numbers after place&route.  Also this may not be the actual minimum period for the design if you are limited by input and output timing.  It only calculates the worst case path timing from clock edge to clock edge for flip-flops within the design.  So if you have a path consisting of external input to flip-flop through look-up table to another flip-flop to an external output, only the path from the first flip-flop through the look-up table to the second flip-flop is measured for "Minimum period".

what exactly does "Maximum pin delay" measure, and can i use it as a performance measure?

I didn't see this in the report, but "Minimum input arrival before clock" is the required setup time from the worst case top-level design input to the clock.  In your case it is less than the "Minimum period" so it may be possible to run the design at the maximum clock frequency specified.  Again after synthesis these are only estimates, you need to place and route the design to get hard numbers.  Also if your design as synthesized represents only a portion of a larger design, the input and output timings may be significantly different, as they may not represent signals going on or off of the FPGA.  Similarly  "Maximum output required time after clock" refers to the delay from the clock to external outputs of the top-level design for the worst case pins.

HTH,
Gabor

-- Gabor
Visitor
Posts: 4
Registered: ‎09-23-2007

Re: Synthesis Help

Thank you very much for your quick and very helpful reply.

"Maximum pin delay" is found in the Place & Route Report.

so in general, if i have 2 algorithms, the first with a Minimum period of 4ns and the second with a Minimum period of 7ns. then this means that Algorithm 1 can run at a faster clock than Algorithm 2, right?

does this mean that i can use the "Minimum period" as a performance measure instead of "Maximum combinational path delay"?

Thanks again...

Regards,
Saed Swedan


Visitor
Posts: 4
Registered: ‎09-23-2007

Re: Synthesis Help

this is an addition to the previous post.

My implementation consists of 3 main modules, a Control Unit (CU), an Register Unit (SU), an Adder Unit (AU), and a Top level Module to connect them all. CU and RU are squential (Clocked), and AU is completely combinational.

My problem is that when I Synthesize the Top level Module I get:
"
   Minimum period: 4.129ns (Maximum Frequency: 242.202MHz)
   Minimum input arrival time before clock: 2.961ns
   Maximum output required time after clock: 2.570ns
   Maximum combinational path delay: No path found
"

And when I Synthesize AU I get:
"
   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 23.301ns
"

So, My Question is, If "Minimum period" could be used instead of "Maximum combinational path delay", shouldn't the "Minimum period" for the Top Level be Larger than "Maximum combinational path delay" for the adder unit? and if "Minimum period" can't be used instead of "Maximum combinational path delay", what should i do?

Please reply asap, this is an urgent matter...

Thanks in advance....

Regards,
Saed Swedan
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Synthesis Help

The minimum clock period depends on paths that go from the Q output of a flip-flip to the D input of another flip-flop in the design.  Not knowing how you hooked up your AU I can't say whether this maximum combinatorial delay is in such a path.  The worst case path may in fact not be connected at the top level.  You would need to look at a static timing report to see what the path is and whether you use it.  Your best bet is to look at the static timing for the top level design and make sure that the AU is in fact included at all.  Also note that the timing reported by synthesis is a best-guess estimate of the achievable timing after place and route.  This is usually only useful when designing reusable IP for example or some other subsystem you would like to know the possible best case speed of.   The real timing performance of a design is only known after place & route and can be found in the post P&R static timing report.  Using the advanced properties for static timing report generation you can get a verbose report that includes uncovered paths in case there are critical paths that have not been constrained.

One other note.  If you look at the maximum paths through AU by synthesizing it separately, you will only get meaningful numbers if you turn off "add I/O buffers" in the synthesis options.  This option is checked by default because normally you build a complete system for the FPGA.  In the case of an internal subsystem, the IOB timing could add a significant delay to your maximum combinatorial path.  This could in fact be the reason your top level clock period is faster than the AU maximum combinatorial delay from the report.

HTH,
Gabor
-- Gabor
Highlighted
Visitor
Posts: 4
Registered: ‎09-23-2007

Re: Synthesis Help

Thanks gszakacs for your reply i'll test it and see.

Regards,
Visitor
Posts: 9
Registered: ‎06-05-2008

Re: Synthesis Help

Can you please again highlight on the message "Maximum combinational path delay: No path found".

 

I am get this message in synthesis report of few of my designs..

 

Do you mean that we get this message when there is pure combinational circuit between the input and output of the design???

Adventurer
Posts: 55
Registered: ‎03-06-2011

Re: Synthesis Help

You got this message when there is no combinational circuit between top module inputs and outputs of the design. All of the inputs goes to output through syncronous elements.