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2,992 Views
Registered: ‎01-22-2015

BRAM address pipelining

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For Block Memory (BRAM) IP in 7-Series FPGA, there are optional pipeline stages/registers (ref PG058).   These registers are located near muxs found in the data output circuitry of the BRAM as shown by Cx_regs in the simplified BRAM sketch below. 

 

BRAM_IP.jpg

 

I find that the address paths into the BRAM sometimes fail timing analysis.   Hence, I sometimes need pipeline registers shown as Bx_regs in the sketch.  However, BRAM IP has no provision for these registers.    Is there some way to insert the Bx_reg registers into BRAM IP?        PS. I am instantiating (not inferring) the BRAM IP.

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Scholar jmcclusk
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Registered: ‎02-24-2014

Re: BRAM address pipelining

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try this:

 

phys_opt_design -force_replication_on_nets [get_nets  <wildcard name for your address nets>]

 

before trying this, be absolutely sure you have the right wildcard netname specification for your address nets.   Load the synthesized design into Vivado and run  "puts [get_nets  name..]"  until you are satisfied you have all the nets that need duplication.

 

 

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Scholar jmcclusk
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Registered: ‎02-24-2014

Re: BRAM address pipelining

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Add the 2nd stage registers (the B registers) as a single register stage in your RTL in front of the BRAM IP, and then enable physical design synthesis after placement.    VIvado should be able to replicate the B registers in all the right places.

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Registered: ‎01-22-2015

Re: BRAM address pipelining

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Hi Jim,

 

Thanks for your reply!

 

   Add the 2nd stage registers (the B registers) as a single register stage in your RTL in front of the BRAM IP,

   and then enable physical design synthesis after placement.

I added the register and enabled Post-Place Phys Opt Design as shown below.

phys_opt_design.jpg

 

 

   Vivado should be able to replicate the B registers in all the right places.

Nope

 

I fiddled with adding registers on both the input and output of the BRAM.   Registers placed on the output “pull in” as you say.   Registers placed on the input do not pull-in (and do not replicate).

 

Avrum and I recently talked about something similar for the DSP48.  On the DSP48 input and output there are registers already inside the DSP48 that can be enabled or disabled.   When an external register is “pulled in” to the DSP48, this external register is removed from the netlist and one of the registers internal to the DSP48 is enabled.   This also seems to be what happens on the output of the BRAM IP.

 

However, what we want to happen on the input to the BRAM IP seems to be different.   The registers that we want do not already exist inside the BRAM.  Therefore, we should perhaps not expect register “pull in” to occur on the BRAM input?  

 

Please note that I am instantiating and not inferring the BRAM IP – and prefer to instantiate.

 

Now what?                        

 

PS. I will be away from my computer for a few days – but look forward to your response.

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Registered: ‎01-22-2015

Re: BRAM address pipelining

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Jim,

 

I read from ug904 that Phys_Opt only does stuff when the design has negative slack.   I was testing it on design that was already passing timing analysis.  

 

It seems that Phys_Opt is a different mechanism than the register pull-in that Avrum and I discussed for the DSP48?  -because register pull-in for the DSP48 happened whether or not the DSP48 needs to be pipelined.

 

Anyway, when I return in a few days, I’ll test Phys_Opt on a design that fails timing analysis and see if it will pull-in and replicate registers to pipeline the address input lines for BRAM IP.

 

Thanks,

Mark

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Registered: ‎01-22-2015

Re: BRAM address pipelining

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Hi Jim,

 

   Vivado should be able to replicate the B registers in all the right places.

Still nope!

 

My Vivado project has (WNS = -0.09ns, Failed Endpoints = 33), all associated with a large BRAM (8 x 262144).  The schematic below from the implemented design shows an address-line path into the BRAM that is failing timing analysis.  Two registers are sitting just outside the BRAM that could have been pulled-in, but were not when Post-Route Phys_Opt was enabled by set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]”.

 

BRAM1.jpg

 

Again, I find that registers are pull-in on the data outputs of the BRAM, whether or not Phys_Opt is enabled and whether or not the data output paths have negative slack.  This is good (in my opinion) but does not help solve negative slack on address inputs to BRAM.

 

Is there another way to pipeline the address inputs to BRAM?   -other than manually assembling the big BRAM from smaller BRAM and placing registers and muxes as needed – ugh.

 

Mark

 

 

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Scholar jmcclusk
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Registered: ‎02-24-2014

Re: BRAM address pipelining

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try this:

 

phys_opt_design -force_replication_on_nets [get_nets  <wildcard name for your address nets>]

 

before trying this, be absolutely sure you have the right wildcard netname specification for your address nets.   Load the synthesized design into Vivado and run  "puts [get_nets  name..]"  until you are satisfied you have all the nets that need duplication.

 

 

Don't forget to close a thread when possible by accepting a post as a solution.
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Registered: ‎01-22-2015

Re: BRAM address pipelining

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Thanks!

 

Here's what I did from the Vivado IDE/GUI:

 

I opened the synthesized design and typed the following into the Tcl Console:

                   puts [ get_nets {addrb[*]} ]

 

-and got a list of all the address lines going into the BRAM.

 

I closed the synthesized design, opened the implemented design, and typed the following into the Tcl Console:

                   phys_opt_design -force_replication_on_nets [get_nets {addrb[*]}]

 

-and I got the following error:

                  ERROR: [Vivado_Tcl 4-265] Option -force_replication_on_nets is specified but not supported yet for post-route physical synthesis. Please remove the option and rerun phys_opt_design

 

Did I not follow your instructions properly?

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Scholar jmcclusk
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Registered: ‎02-24-2014

Re: BRAM address pipelining

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Oh..   did you try this on a design that is already routed?    That won't work..   This has to be done after placement, and before routing.

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Registered: ‎01-22-2015

Re: BRAM address pipelining

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WITHOUT POST PLACE PHYS OPT:

#Tcl commands used to run implementation
launch_runs impl_1 -jobs 6
link_design -top TOP -part xc7k160tfbg484-3
opt_design
report_drc -file TOP_drc_opted.rpt -pb TOP_drc_opted.pb -rpx TOP_drc_opted.rpx
place_design
route_design
report_drc -file TOP_drc_routed.rpt -pb TOP_drc_routed.pb -rpx TOP_drc_routed.rpx
report_methodology -file TOP_methodology_drc_routed.rpt -pb TOP_methodology_drc_routed.pb -rpx TOP_methodology_drc_routed.rpx

before_phys_opt.jpg

 

 

 

 

WITH POST PLACE PHYS OPT:

impl_settings.jpg

#Tcl commands used to run implementation
launch_runs impl_1 -jobs 6
link_design -top TOP -part xc7k160tfbg484-3
place_design
phys_opt_design -force_replication_on_nets [get_nets {addrb[*]}]
route_design
report_drc -file TOP_drc_routed.rpt -pb TOP_drc_routed.pb -rpx TOP_drc_routed.rpx
report_methodology -file TOP_methodology_drc_routed.rpt -pb TOP_methodology_drc_routed.pb -rpx TOP_methodology_drc_routed.rpx

after_phys_opt1.jpg

 

after_phys_opt2.jpg

 

Registers replicated – WOW!

BRAM address inputs pipelined – WOW!!

Timing closure achieved – WOW!!!

In my happy place – WOW!!!!

-many thanks !!!!!

 

Mark