09-23-2017 11:08 AM
I'm trying to use a single port ram using IP modules however I'm getting the above warning and there is no IP module generated in the end. I'm also using clock core IP which is working properly. So could anyone explain how to generate a memory block IP module ?
p.s : Some people suggest using core generator (tools -> core generator ...) and uncheck ASY generation. But this generates a new project in my current project and I don't know how to proceed. There are two files generated a vhdl model of the bram and a " .ngc " file (I couldn't achieve to open). So I don't know what to do with this ngc file.
p.s 2: I'm using ubuntu 16.04
p.s 3: Complete warning message : WARNING:sim:946 - Failed to initialise IP Model for ASY schematic symbol
Thanks in advance
09-23-2017 11:42 AM
I'm trying to use a single port ram using IP modules ...
Are you referring to a BRAM you want to use in a block design here?
If so, what size/interface do you want/need?
There are two files generated a vhdl model of the bram and a " .ngc " file
(I couldn't achieve to open). So I don't know what to do with this ngc file.
The NGC file is a netlist with constraint information.
It is usually included in implementation or simulation.
09-24-2017 09:29 PM
09-25-2017 04:22 AM
09-25-2017 04:31 AM