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Adventurer
Adventurer
1,763 Views
Registered: ‎01-26-2017

Large dual-port BRAM reads (Native) does not read every cycle

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Hi there,

 

I am having some trouble using BRAMs as 5 row buffers stuck together. I have dual port BRAM that is writing 14 bit data in on the A port, and reading out 448 bit data on the B port, which is constructed into a 5x5 kernel for later use. The issue I am having is that my reads should occur every cycle as the kernel "slides across" the row buffers, but the problem is that the output data changes only every 8 cycles. 

 

I have attached some screenshots to explain my design. Checking the screenshot, it is clear that my reading and writing should be done by incrementing by the size of my kernel (which is 5 in this case). I.e on first cycle, read_addr = 0, then on 2nd, read_addr = 5 etc.  

 

And then the waveform output does not change every cycle, however notice that the output is a zero matrix at address 40 as expected. This is very confusing to me, my wr_en and rd_en are constant on their respective ports, otherwise I would say this is just that my rd_en is being held low for 8 cycles etc or my din on the write port is held constant by accident. Does anyone have any ideas?

 

Thanks for your time.

--- Estimated Development time: 2*Pi*(planned completion date) ---
Tags (3)
bram_reads.PNG
memory structure.PNG
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1 Solution

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Voyager
Voyager
1,997 Views
Registered: ‎03-28-2016

Re: Large dual-port BRAM reads (Native) does not read every cycle

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I believe it's an issue with the architecture of the BRAMs.  In the systems that I have worked on, I always see the use of individual fifos (line buffers) and then a set of registers to hold the active data.

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
11 Replies
Explorer
Explorer
1,750 Views
Registered: ‎07-17-2014

回复: Large dual-port BRAM reads (Native) does not read every cycle

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@aaron_holliday

Because the width of the read side is 32 times that of the write side (448/14), the address of the reading side corresponds to the 32 address of the write side, that is to say, the data of the 5x5 can be read in a clock cycle.

So the reading side does not need to read continuously.

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Adventurer
Adventurer
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Registered: ‎01-26-2017

回复: Large dual-port BRAM reads (Native) does not read every cycle

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@avcon_lee the data does need to be read continuously, the kernel moves every single cycle. My question is why the BRAM output does not change every cycle

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Explorer
Explorer
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Registered: ‎07-17-2014

回复: Large dual-port BRAM reads (Native) does not read every cycle

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@aaron_holliday

One question is that even if you write the kernel data in advance, the write side takes 5 clock cycles to move a kernel,and the reading side needs to wait for the 5 clock to do the next operation.

Is the efficiency not very slow?

 

As for Bram, why not every clock is changing, it depends on what you wrote to BRAM.

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Adventurer
Adventurer
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Registered: ‎01-26-2017

回复: Large dual-port BRAM reads (Native) does not read every cycle

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@avcon_lee it would take 5 cycles to move across for a whole kernel, but in image processing, the kernel often overlaps. I need to read every cycle so that I can read in the manner explained in the attachment. The data written to the BRAM is shown in the attachment also. It is being written with values on every clock cycle, yet the data does not change every clock cycle

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Explorer
Explorer
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Registered: ‎07-17-2014

回复: Large dual-port BRAM reads (Native) does not read every cycle

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@aaron_holliday

The waveform above is the result of simulation or the operation of the real machine?

and What is the use of the line_resetter[2:0] signal in the waveform?

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Adventurer
Adventurer
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Registered: ‎01-26-2017

回复: Large dual-port BRAM reads (Native) does not read every cycle

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that is rtl simulation. line resetter is used to reset addresses and to rearrange kernel depending on how many lines have been read

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Voyager
Voyager
1,698 Views
Registered: ‎03-28-2016

Re: Large dual-port BRAM reads (Native) does not read every cycle

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I don't think you can use the BRAMs in the manner that you illustrate.  Check out the section on aspect ratios (pg. 48) in the following user guide.

 

https://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_4/pg058-blk-mem-gen.pdf

 

Basically, each port can only handle data in units that match it's size.  If a port is 1-byte wide it can handle 1-byte transactions.  For example write byte_0, byte_1, byte_2, byte_3.  If a port is 4-bytes wide it can only handle 4-byte transactions.  For example read bytes 0,1,2 and 3 or read bytes 4,5,6 and 7.  It can't read bytes 2,3,4 and 5.

 

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Adventurer
Adventurer
1,671 Views
Registered: ‎01-26-2017

Re: Large dual-port BRAM reads (Native) does not read every cycle

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Hi @tedbooth

 

Would I be able to overlap my reads if I am not using byte-writes and byte reads? Or is it architecture-related to the memory and I need a new method to allow burst reads?

 

I know that I can achieve same functionality with 5 FIFOs and a few registers, but that is slightly messier

 

Thanks

--- Estimated Development time: 2*Pi*(planned completion date) ---
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Explorer
Explorer
1,661 Views
Registered: ‎07-17-2014

Re: Large dual-port BRAM reads (Native) does not read every cycle

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@aaron_holliday

Can you put the waveform that write address from 0 to 3 and from 20 to 23 up ? 

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Voyager
Voyager
1,998 Views
Registered: ‎03-28-2016

Re: Large dual-port BRAM reads (Native) does not read every cycle

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I believe it's an issue with the architecture of the BRAMs.  In the systems that I have worked on, I always see the use of individual fifos (line buffers) and then a set of registers to hold the active data.

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Adventurer
Adventurer
1,042 Views
Registered: ‎01-26-2017

Re: Large dual-port BRAM reads (Native) does not read every cycle

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Thanks Ted, this has been very helpful. Kudos and solved.

--- Estimated Development time: 2*Pi*(planned completion date) ---
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