UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Newbie anoancea
Newbie
8,344 Views
Registered: ‎08-27-2014

Soft Error Mitigation Controller (SEM) : Difference between linear and physical frame address, and the respective location in the bitfile

Hello,

 

I recently had the opportunity to expose an Artix 7 (XC7A200T) FPGA to radiation, and implemented the LogiCORE SEM IP Core to counter bit flips. The SEM Controller has a UART interface which reports a maximum frame of 0x000049D7. 

Here is an example of a correction report:

 

[...]

PA 004434A0

LA 0000477A

[...]

 

Is the physical address (PA) the same as the frame address (does each bit correspond to the bits of the FAR described in the Configuratino User Guide)?

 

In a typical (uncompressed) bitfile, the frame address is first set to 0 and then it auto increments while the CLB frame data is pushed into the FDRI. However I do not know how it increments. How can I map the reported frame to the respective frame inside the bitfile?

 

I would appreciate any help or feedback,

 

Cheers,

 

Andrei

0 Kudos
1 Reply
Scholar austin
Scholar
8,330 Views
Registered: ‎02-27-2008

Re: Soft Error Mitigation Controller (SEM) : Difference between linear and physical frame address, and the respective location in the bitfile

a,

 

Please let me know what it is you wish to do.  I provide support for unuiversities, researchers in performing their radiation testing.  I cannot share the details you asaked for, but I am able to parse your readback files, and report back to you exactly what flipped.  In this way, all data and papers submitted for publication reflect actual facts, and are not subject to mis-interpreted, or distorted.

 

austin@xilinx.com

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos