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Participant fhknapp44
Participant
3,390 Views
Registered: ‎02-25-2015

C512 with ISE 14.7

Can someone look at this project for anything obvious that would contribute to implementation problems? The system only allowed me to attach these 6 files, leaving 2 small files. If you need them I will post seperatly.

FHK

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6 Replies
Scholar pratham
Scholar
3,385 Views
Registered: ‎06-05-2013

Re: C512 with ISE 14.7

@fhknapp44 Why dont you archive and attach your project here? By the way what is the error messgae ?

-Pratham

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Participant fhknapp44
Participant
3,372 Views
Registered: ‎02-25-2015

Re: C512 with ISE 14.7

Prathem: OK, here is the ZIP generated by ARCHIVE.

The frustrating part is when the implementation 'breaks' there are no direct error or suspicious warning messages.

FHK

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Xilinx Employee
Xilinx Employee
3,364 Views
Registered: ‎08-02-2007

Re: C512 with ISE 14.7

hi,

 

that is strange behavior. i was able to compile the design without any errors.

 

attached is the FIT report.

 

would that be possible to share the screen shot of the Project Navigator when the FIT fails?

What is the OS that you are using at your end?

 

--hem

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Participant fhknapp44
Participant
3,349 Views
Registered: ‎02-25-2015

Re: C512 with ISE 14.7

Hem: I does compile without errors. It is just that functionality gets broken in different places that change with each 'repair'. Going nuts with 'No Reduce' helped but was not a cure-all.
FHK
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Participant fhknapp44
Participant
3,343 Views
Registered: ‎02-25-2015

Re: C512 with ISE 14.7

Take a look at the Synthesis Messages, Can not figure out why sequencial bus members are in conflict. XLXN_32, XLXN_43, OFF_BaseValue, ON_BaseValue, XLXN_436, 437, 438,439,440 and 441 are all in self conflict.

FHK

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Participant fhknapp44
Participant
3,331 Views
Registered: ‎02-25-2015

Re: C512 with ISE 14.7

OK, now i have made a small simplification, changing a FDCP for a FDC and reassigning the signal sources of 3 output pins, and the fitter can't get the design into the device.

FHK

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