06-15-2015 10:03 AM
Can someone look at this project for anything obvious that would contribute to implementation problems? The system only allowed me to attach these 6 files, leaving 2 small files. If you need them I will post seperatly.
06-15-2015 10:18 AM
@fhknapp44 Why dont you archive and attach your project here? By the way what is the error messgae ?
06-15-2015 01:58 PM
Prathem: OK, here is the ZIP generated by ARCHIVE.
The frustrating part is when the implementation 'breaks' there are no direct error or suspicious warning messages.
06-15-2015 06:46 PM
that is strange behavior. i was able to compile the design without any errors.
attached is the FIT report.
would that be possible to share the screen shot of the Project Navigator when the FIT fails?
What is the OS that you are using at your end?
06-16-2015 08:22 AM
06-16-2015 02:20 PM
Take a look at the Synthesis Messages, Can not figure out why sequencial bus members are in conflict. XLXN_32, XLXN_43, OFF_BaseValue, ON_BaseValue, XLXN_436, 437, 438,439,440 and 441 are all in self conflict.
06-16-2015 09:12 PM
OK, now i have made a small simplification, changing a FDCP for a FDC and reassigning the signal sources of 3 output pins, and the fitter can't get the design into the device.