07-03-2015 12:22 AM
I have a test a configuration on the X9500 cpld in order to implement some protection functionalities and control of some ventilation relays. For the protection functionality is using some flip flops to latch the error condition acquired by input pins and disconnect the outputs.
The board is designed correctly and follows the normal design practices and the power supply is decoupled and filtered. The output relays will switch some power relays and fans and a noise generated by the close operation of these contactors is expected. The rest of the board and the microprocessor are operating with any problems.
However, when the power relays close, the CPLD flip flops are triggered, even if the inputs are pulled up directly to VCC. I cannot explain this, because even if I wire an input directly to VCC and if I program a flip flop with the clock transition associated to that pin, the flip flop output shouldn’t change status. But is changing status when the power relays and fan close…
There is some explanation for this strange behavior?
07-03-2015 08:39 AM
Relays are inductors. Inductors create magnetic fields. Magentic fields couple to wires and induce voltages (transformer action).
First, the relay should have proper transient suppresion on the coil: a diode to the supply across the coil to absorb the kick-back when it shuts off. Second, a series RC network to suppress the rise and fall time to reduce emissions. Third, the contacts also need RC suppresion.
It is unlikely you will actually see the transient, as it may be as fast a a few gigahertz. It will upset the CPLD, and my cuse it to lose its programming.
You may need farady shield around the circuits, to isolate it from the relays (for large relays), or use relays with shields around them.
A shorted turn (shield) around the relay will reduce emmitted fields, for example.
07-03-2015 11:13 PM
Thank you for your comments. I cannot change the noise emission. I must work onn the immunity side.
The cpld input detects a small transient and triggers the flip flop. That seems to be the cause of this problem. There is something that can be done on the cpld programming to be more robust to this effect?
For instance, some delay or counter with a minimum consumption of macrocells? Unfonrtunately, the board is not equipped with a oscillator generator for the cpld...
07-04-2015 07:52 AM
That is unfortunate. You need external noise suppresion filters at the inputs (RC neworks).
Trying to fix in the CPLD without a clock just will not work in my opinion.
With a clock, you may be able to count how long an input is asserted to rejeck noise.