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Adventurer
Adventurer
329 Views
Registered: ‎05-03-2018

Artix-7 does not reconfigure itself properly at a short power dip

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This question is about the Xilinx Artix-7 (XC7A75T-2FTG256I) FPGA.

*From our customer*
"
We see a problem where the FPGA does not reconfigure itself properly at a short power dip.
What we observe is that the DONE pin becomes low during the dip, and remains low after the dip.
If we reconfigure the PROGRAM_B pin again after the dip, the FPGA will reconfigure itself.

I have added the relevant part of the diagram.

Measurements/tests we have done:

  • Power supply voltages during dip where the problem occurs.
    o See supply voltages.png: CH1: 3V3, CH2: 3V3_VCCO, CH3: 1V8, CH4: 2V5.
    o During the dip, the VCCAUX, VCCBRAM and VCCINT, go to 0V. At VCCO a respiration of ~1V remains.
    If we discharge the VCCO during the power dip we don't see the problem. We do not see this as a structural solution, because we do not understand the problem.
    o If we look at the SPI lines of the configuration flash we see no activity on it when the problem occurs.
  • Program_b
    o See program_b.png: CH1: 3V3, CH2: 3V3_VCCO, CH3: Progam_b, CH4: 2V5
    o Program_b is operated by the supply supervisor. We see that this goes down nicely when the supplys are out of regulation and 10ms after everything is up again.
  • Init_b
    o See program_b-and-init_b.png: CH1: 3V3, CH2: 3V3_VCCO, CH3: Progam_b, CH4: INIT_B
    o Based on UG470 (Table 2-4; note on PROGRAM_B text) we tried to keep both program_b and init_b low during the dip event. Unfortunately this also has no effect

Could you help us with the following questions?

  • What can make the FPGA not execute a POR sequence / not reconfigure itself?
    o Keep PROGRAM_B and INIT_B low should trigger a POR?

"

I already try to explain some of the issues:
POR is not the same as pulling the PROGRAM_B
POR starts at phase1, doing some housekeeping,
while pulling PROGRAM_B returns to phase2 and assume the Artix-7 is in a well defined state.


In my opinion it is not after a power dip, besides this Vcco is not completely down and causing issues as the have noticed themselves. Should be parasitic supply from Vcco to other internal rails disturbing a correct POR.

I already asked for the minimum down-times, although not specified by Xilinx, this can give us some clues.

Although an Artix-7 is involved I am not convinced that it is a real Xilinx problem,
I think it is out of specification and they should rework their power supply.

- After I asked some info an had a talk with him here's the answer from our customer:

"

The power dip takes about 200~250ms, during this time the Vccint, Vccbram and Vccaux are below 0.5V (for about 150ms~200ms they are almost 0V).
Risk time per power supply is 1ms and delay between each power supply is 20ms.

We don't have to perform a real POR so much.
Our initial idea was to start a reconfiguration by toggling program_b (as in figure 5-5 in ug470),
because the voltages have fallen below the minimum data retention voltages.
Either program_b low when the power supplies are too low and program_b high when the power supplies are 20ms (high) stable.

According to table 2-4 of ug470 program_b edge is triggered, FPGA configuration is cleared on falling edge and reloaded on rising edge. The problem is that the voltages at the time when we pull the program_b low are outside spec.

"

Does Xilinx have a reference design how to deal with short power dips,
or reconfiguration after 1 or more power rails have fallen away?

Thanks in advance for your help.
Best regards,
Andrea

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Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎03-07-2018

Re: Artix-7 does not reconfigure itself properly at a short power dip

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Hi @andreac_avnet

Holding INIT_B pin to low during power-up can delay the power-on configuration of the FPGA. 

I will recommend holding only INIT_B pin to low on power up and release it after power supplies become stable.

Note: Holding PROGRAM_B Low from power-on does not keep the FPGA configuration in reset. Instead, use INIT_B to delay the power-on configuration sequence.

Regards,
Bhushan

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1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎03-07-2018

Re: Artix-7 does not reconfigure itself properly at a short power dip

Jump to solution

Hi @andreac_avnet

Holding INIT_B pin to low during power-up can delay the power-on configuration of the FPGA. 

I will recommend holding only INIT_B pin to low on power up and release it after power supplies become stable.

Note: Holding PROGRAM_B Low from power-on does not keep the FPGA configuration in reset. Instead, use INIT_B to delay the power-on configuration sequence.

Regards,
Bhushan

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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