UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
12,216 Views
Registered: ‎02-08-2013

BPI Flash config / EMCCLK BitGen Opt

Jump to solution

Hi all,

 

I'm using Planahead 14.6 on windows 64-bit.

 

Previously, on earlier versions of Planahead I could use the BitGen options ExtMasterCclk_en:Yes and ExtMasterCclk_divide:2 to create a bitstream that I could run through PromGen and create a bootable flash image (.mcs file) for the BPI flash on the KC705 Dev board. Nice and straight forward.

 

On this version of Planahead the _divide option seems to be depreciated, and instead I have one BitGen Option:

 

-g ExtMasterCclk_en:div-2

 

Only now I get the following error:

 

ERROR: Bitgen:347 - Pin R24 is the EMCCLK pin and must be programmed as an input
when the ExtMasterCclk_en option is not set to Disable. This pin is in bank
14 which has no required Vcco voltage.


ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.

 

I did add the EMCCLK to my top level with the correct pinout and IOSTANDARD, but that seems to get optimized out. Am I supposed to now instantiate the STARTUPE2 component and tie the EMCCLK to this? Do I then need to specify other config pins to attatch to that primative?

 

I got the impression from the Config PDF and everything else that came up while searching for an answer, that the STARTUPE2 block was for giving control of the spi flash to user logic post configuration?

 

 

0 Kudos
1 Solution

Accepted Solutions
Adventurer
Adventurer
18,635 Views
Registered: ‎02-08-2013

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

So I finally got round to getting this to work, (It seems I had two problems):

 

1) Double checked the jumper settings on the Eval board and they were inverted to what they should be, below is the configuration setting I set it to (D/ down being the dip switch set towards the number on the dip casing):

 

D   D    D   U   D

1    2    3    4    5

 

2) An option I never had to use in previous versions of BitGen needs setting, for the flash device on the board:

 

-g bpi_sync_mode:Type2

 

3) I did have to assign EMCCLK in the top level of  my design as an input, and assigned it to the appropriate pin on the KC705 board (pin R24).

 

Then I followed my old instructions of creating a .mcs ROM file from the .bit file output by BitGen.

 

11 Replies
Xilinx Employee
Xilinx Employee
12,209 Views
Registered: ‎01-03-2008

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

The ERROR message indicates that the pin (R24) must be an input when using this configuration option.  Is it an input in your design?

 

Note: This is posted in the wrong forum.  It should be posted in one of the family named sub-forums.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
Adventurer
Adventurer
12,205 Views
Registered: ‎02-08-2013

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

I'm specifically using the KC705 so I thought Boards and Kits would be the place for it - I guess I wasn't that explicit. 

 

As I stated:

 

I did add the EMCCLK to my top level with the correct pinout and IOSTANDARD, but that seems to get optimized out. Am I supposed to now instantiate the STARTUPE2 component and tie the EMCCLK to this? Do I then need to specify other config pins to attatch to that primative?


Adding it as a port (do I just specify it as a port that connects to nothing?) and adding it to the UCF does allow BitGen to complete, but when I follow the same procedure to create the mcs file, as I've done countless times when I used the previous BitGen options, it won't boot and the INIT light on the dev board goes red.

0 Kudos
Xilinx Employee
Xilinx Employee
12,194 Views
Registered: ‎01-03-2008

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

> I'm specifically using the KC705 so I thought Boards and Kits would be the place for it

 

While you are using the KC705 the problem that you are having has nothing to do with using the board.

 

The EMCCLK is for using an external clock for master mode configurations.  If you are not also using this pin post-configuration as a input clock then nothing should be done to your design (no port, no connections).

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
Adventurer
Adventurer
12,188 Views
Registered: ‎02-08-2013

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

"no port, no connections"

 

So this brings me back to my original question - what is the method for compiling a bitstream to be turned into a bootable flash image on the KC705 dev board?

 

The method I used to use using the documentation no longer works as one of the BitGen options is depreciated, and using the recommended option from the latest programmer tools manual, I get a BitGen error saying I need to configure EMCCLK as an input?

0 Kudos
Adventurer
Adventurer
12,187 Views
Registered: ‎02-08-2013

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

is there any way to move this to the appropriate topic?

0 Kudos
Xilinx Employee
Xilinx Employee
12,178 Views
Registered: ‎02-27-2014

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

In your top-level, define emcclk as input port and add the following lines to your XDC file, by appropriately passing desired values:

 

# for Quad SPI
set_property BITSTREAM.CONFIG.BPI_BUSWIDTH 4 [current_design]
# Sets the EMCCLK in the FPGA to divide by 1
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-4 [current_design]

 

-AAV-

0 Kudos
Adventurer
Adventurer
12,170 Views
Registered: ‎02-08-2013

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

Hi aav,

 

I'm using planahead and my constraints are in ucf format - I have specified the div clock as a BitGen option using the GUI like so: -g ExtMasterCclk_en:div-2

 

As I'm using the KC705 eval board I believe the external clk (66MHz) needs dividing by 2 to 33MHz? This is what speed I had it running at before the BitGen options changed between versions of Planahead/ ISE.

 

Interesting addition of the BusWidth, I'll check out BitGen options for that. 

 

0 Kudos
Adventurer
Adventurer
18,636 Views
Registered: ‎02-08-2013

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

So I finally got round to getting this to work, (It seems I had two problems):

 

1) Double checked the jumper settings on the Eval board and they were inverted to what they should be, below is the configuration setting I set it to (D/ down being the dip switch set towards the number on the dip casing):

 

D   D    D   U   D

1    2    3    4    5

 

2) An option I never had to use in previous versions of BitGen needs setting, for the flash device on the board:

 

-g bpi_sync_mode:Type2

 

3) I did have to assign EMCCLK in the top level of  my design as an input, and assigned it to the appropriate pin on the KC705 board (pin R24).

 

Then I followed my old instructions of creating a .mcs ROM file from the .bit file output by BitGen.

 

Contributor
Contributor
11,077 Views
Registered: ‎05-17-2009

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

This sounds similar to the document I used as a crib sheet (the xtp106 tutorial .PDF for the KC705 PCI Express project:

 

@echo off

rem
rem Create PROM file suitable for transfer to KC705 board
rem
rem Derived from KC705-pcie-pdf-xtp106-14.4.pdf
rem

bitgen -w -g BPI_sync_mode:Type2 -g ExtMasterCClk_en:div-2 -g Compress kc705_fmc164.ncd kc705_fmc164_prom.bit
if errorlevel 1 goto bail

promgen -w -p mcs -c FF -s 131072 -u 0 kc705_fmc164_prom.bit -bpi_dc parallel -data_width 16
if errorlevel 1 goto bail

rem
rem Burn the PROM
rem

impact -batch mkprom_impact.cmd

:bail

My Impact command file looks like this:

 

setMode -bs
setCable -port auto
Identify -inferir
identifyMPM
attachflash -position 2 -bpi "28F00AP30"
assignfiletoattachedflash -position 2 -file "kc705_fmc164_prom.mcs"
Program -p 2 -dataWidth 16 -rs1 25 -rs0 24 -bpionly -e -v -loadfpga
closeCable
quit

Seem kind of goofy that there is no other canonical document anywhere (that Google can find) that explains how to set up a bootable KC705 configuration, but that's the way Xilinx rolls.  Even though you solved your issue I'll drop this here for future reference (possibly even my own)...

0 Kudos
Adventurer
Adventurer
10,272 Views
Registered: ‎02-08-2013

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

Excellent work with the scripts! 

 

I agree that if specific options change in succesive versions of the software the docs should reflect that somewhere - I know the latest UG628 Devref guide documents the option itself, but the KC705 manual makes no mention of it. It's also why I think this thread is more specific to the KC705 eval board, than the generic Design Tools.

 

At least there is a record now. 

0 Kudos
Newbie wdooy
Newbie
9,960 Views
Registered: ‎08-07-2014

Re: BPI Flash config / EMCCLK BitGen Opt

Jump to solution

hi,看了半天也没有具体弄明白! 最后的结果是通过在顶层加输入一个无效的端口EMCCLK作为输入吗? 然后其他的bit配置按照ise手册中配置进行配置?

0 Kudos