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Visitor marctroost
Visitor
90 Views
Registered: ‎11-27-2018

Device reconfiguration after power dip

Hello,

In a design of ours we are using a Artix 7 FPGA (XC7A75T-2FTG256I). Device is powered using 1V0 for VCCINT and VCCBRAM, 1V8 for VCCAUX and 2V5/3V3 for VCCO (VCCO_0 = 3v3). We have enable the in order VCCINT+VCCBRAM -> VCCAUX -> VCCO, slew rate of each supply is 1ms, 20ms delay between enabling of each supply. We use a supply supervisor to pull the PROGRAM_B pin low in case when one of the supplies is out of regulation.

 

The issue we are observing is that the FPGA does not start a new reconfiguration cycle after a short power dip (~250ms). During this dip 1V0 and 1V8 drop to ~0V, while VCCO drops to ~1V. After the dip, when all supply voltages are within specification, we release PROGRAM_B high again. However, no communication is observed on the serial configuration flash SPI bus and the DONE pin remains LOW. If we readout the status register, REGISTER.CONFIG_STATUS.BIT18_CFG_STARTUP_STATE_MACHINE_PHASE remains at 000. 

 

What are the recommendations / design guidelines to guarantee a device reconfiguration after one of the supply voltages has (shortly) dipped below the minimum required level?

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Xilinx Employee
Xilinx Employee
75 Views
Registered: ‎03-07-2018

Re: Device reconfiguration after power dip

Hi @marctroost

Do you mean FPGA power dip occurs at the start after Power recycling? If yes, then you can delay configuration by holding the INIT pin Low until power reaches to minimum recommended level of power rail. Check UG470 (v1.13.1) (Page 84) for more details.

Make sure SPI flash is ready to receive commands before the FPGA starts its configuration procedure. To ensure that you can follow system design approaches provided at UG470 (v1.13.1) (Page 58) 

PCB design for your design is finalized? If not, take a look at UG483 (v1.13) and xmp277-7series-schematic-review-recommendations.zip. And also check for 7_Series_XPE_2018_2.xlsm

Regards,
Bhushan

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Visitor marctroost
Visitor
59 Views
Registered: ‎11-27-2018

Re: Device reconfiguration after power dip

Hi @bpatil,

No, the dip occurs (randomly) after the device has completely booted. The dips are a result of a dips and interrupt test on the external main power supply of the system.

The design is in its final stage. We see no issues during normal power-up and long dips.

What we have tried so far:

* keep both PROGRAM_B and INIT_B low during the dip -> no effect

* keep INIT_B low for an additional 20ms after the supplies have stabilized  (SPI flash is able to process commands within 1ms after powerup) -> no effect

* apply extra load to VCCO_0 (have VCCO_0 drop lower (<<1V), during the dip). FPGA reconfigures correctly. This rules out the SPI flash as a source of failure.

 

Based on our tests we think that a ~1V remaining voltage on VCCO_0 keeps the device from correctly starting a POR sequence, even though VCCINT/VCCAUX have dropped to 0V. Is this assumption correct?

As we pull PROGRAM_B low at the moment the supply's are failing, could this cause an issue with the clearing of the FPGA configuration? Which in turn prevents the device from correctly starting a reconfiguration?

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Xilinx Employee
Xilinx Employee
50 Views
Registered: ‎03-07-2018

Re: Device reconfiguration after power dip

Hi @marctroost

Based on our tests we think that a ~1V remaining voltage on VCCO_0 keeps the device from correctly starting a POR sequence, even though VCCINT/VCCAUX have dropped to 0V. Is this assumption correct?

>>> No. The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCAUX have dropped to zero and VCCO_0 is powered up earlier, then it will not follow recommended POR sequence. Better to check combined scopeshots of  VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO at startup.

All supply voltages should be within the recommended operating ranges; any dips in VCCO_0, VCCAUX, VCCBRAM, and VCCINT below recommended voltage specified in datasheet can cause loss of configuration data.

As we pull PROGRAM_B low at the moment the supply's are failing, could this cause an issue with the clearing of the FPGA configuration? Which in turn prevents the device from correctly starting a reconfiguration?

>>> Yes, FPGA Configuration memory is cleared sequentially any time the device is powered up, after the PROGRAM_B pin is pulsed Low

Regards,
Bhushan

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