ERROR: [Labtools 27-3165] End of startup status: LOW

[martindreher]

I can't program the Zynq Ultrascale ZU2EG twice without switch off and on the power.

My steps to reproduce the issue:

1. Power up my board with a ZU2EG on it
2. Vivado -> Hardware Manager -> Program Device
3. Program Device
4. Done LED goes off
5. Xilinx SDK -> Run System Debugger with Option "Run psu_init"
6. Applikation is running
7. ...so far so good

Now, if I restart at point 2 again I get following errors and the Done LEDs doesn't switch off

ERROR: [Labtools 27-3165] End of startup status: LOW
ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors.

if I restart at point 5 I get the following error

[...]
INFO	: Hardware design information is loaded from '[...]/zusys_wrapper_hw_platform_0/system.hdf'.
INFO	: 'configparams force-mem-access 1' command is executed.
INFO	: Context for 'APU' is selected.
INFO	: Sourcing of '[...]/psu_init.tcl' is done.
ERROR	: AP transaction timeout

What I tried:

- Different clock speeds on the JTAG connection

- When I stop after point 4 and restart at point 2 it works. So the problem only occurs after I run the application once.

Do someone known a solution for the problem or how I can figure out where the problem is?

Thanks

[kkn]

you didn't mention which version of the tool you are using?

If you havent tried with newer version i.e.2071.4 hardware manager and SDK, then try with this version and post your results.

[martindreher]

Sorry for that...

Yes, I using the latest version 2017.4

[kkn]

can you check the following AR and try to apply the patch and see if this helps

https://www.xilinx.com/support/answers/70065.html

[martindreher]

Thanks. I saw this answer, but I have to questions to it...

1. Is it fixed in the version 2017.4?

2. Where can I run the command "CSU.pcap_prog{pcfg_prog_b} = 0"? In the Xilinx SDK -> xsct console?

[kkn]

Hi 

this issue seems to be intermittent problem and could not be reproduced in 2017.4 at my end

you can use the readme file in the patch for the instruction of the installation of the patch

--Krishna

[martindreher]

Hi kkn,

thanks for your answer.

Please can you give me a hint where I can run the command "CSU.pcap_prog{pcfg_prog_b} = 0"?

Thanks.

[hegau]

Is there any solution for that issue?

[kkn]

you need to follow the AR mentioned in earlier post to install the patch and then use vivado programmer as mentioned in the readme file

"CSU.pcap_prog{pcfg_prog_b} = 0"? this should not be used in tcl console

[hegau]

I also using Vivado 2017.4. And in the readme of the patch is the sentence "It will no longer be needed as of Vivado 2017.4."
What is correct now?

[evv06001]

Hello,

I am not sure if the following solution will help you out; but I had the same error and this is what I did to solve the problem.

First off, I was using a an Artix7 with S25FL128SAGNFI001 SPI flash. I knew that the JTAG interface that we designed had poor signal integrity, therefore I slowed down the JTAG clock speed. I also realized that I needed to select "pull down" on the "state of non-config meme IO pins" setting. Finally, I was prompted by Vivado Lab that I actually had the wrong part selected, I had picked s25fl128l-spi-x1_x2_x4 from the list of available flash devices instead of s25fl128sxxxxxx0-spi-x1_x2_x4. 

If some of the above applies to your situation, try to tweak some of the setting described above, maybe it will help.

Best!