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Registered: ‎11-11-2012

Feasibility of Partial Reconfiguration - Zynq Z-7020



I've read anything I could about Partial Reconfiguration, but I still have many doubts.

What I'm trying to do is the following:

  • initially program the FPGA with a "loader" written in HDL (FSM + UART interface or other interfaces)
  • the loader receives the new partial bitstream through the UART interface (or another interface)
  • the loader performs some operations on the partial bitstream and then configures the FPGA with it

I have to do these operations on the Zynq Z-7020 without involving the CPU (PS), but only with the PL.

Is that even possible?


I must note that it is very important that the PL is able to perform some operations on the partial bitstream before loading it into the FPGA.



Thanks in advance

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2 Replies
Scholar austin
Registered: ‎02-27-2008

Re: Feasibility of Partial Reconfiguration - Zynq Z-7020



What you descibe is all possible.  I suggest you start by working all the design exercises in:




and examine all the demo designs for a zedboard, or Zynq board of your choice.


The Zynq procesor system starts up with exclusive control of the programmable logic.  After the initial load, the processor may be programmed to turn over control.  The PL may then with a design as you descibe, take over.



Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor hypertext
Registered: ‎11-11-2012

Re: Feasibility of Partial Reconfiguration - Zynq Z-7020

Thanks for the reply.

What I have understood so far is:

  • I have to involve the PS, at least in the first stage (I don't understand why, because with Vivado - or other tools like Adept - I can select to program only the PL, hence leaving the PS "unprogrammed". Is this a Zynq constraint? If so, how can the PS turn over the ICAP control to the PL?)
  • I've read many documents, but I don't understand how to fetch the bitstream into the ICAP primitive. From my understanding, it's the ICAP itself that reads the partial bitstream from the SD. What if my bitstream is coming from the UART port?


Thanks again,


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