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Kintex-7 SPI Master Configuration Fail.

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Observer
Posts: 17
Registered: ‎04-13-2017

Kintex-7 SPI Master Configuration Fail.

Hi all,

 

I designed a board using Kintex-7 FPGA. Only one of several boards has a configuration fail at boot-up. The power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO. The board with the issue has the following symptoms.

The SPI master signals (cs, clk) are output before the Program_B ramp starts. (VCCO ramp is the same as Program_B.)

 

 

temp.png

 

I have some questions.

1. When can this issue occur?
2. What is the threshold voltage of the program_b signal?
3. What is the threshold voltage of VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO (2.5V, 3.3V and 1.8V) in power-on sequence to start the power-on reset?

 

Thanks

 

Scholar
Posts: 2,709
Registered: ‎07-09-2009

Re: Kintex-7 SPI Master Configuration Fail.

[ Edited ]

looks like you have a 50 ms rise time on that prog_b,

 

Whats your vcc ramp time, does it meet the specs ?

 

what size pull up do you have , prog_b needs less than 4k7, I'd usually use 1K 

Observer
Posts: 17
Registered: ‎04-13-2017

Re: Kintex-7 SPI Master Configuration Fail.

Hi drjohnsmith,

 

Thank you for your response.

All VCC ramps are less than 50ms. It seems to satisfy the spec. And the pull-up resistor for prog_b is 4.7 Kohm.

 

Thank you.

 

Scholar
Posts: 2,709
Registered: ‎07-09-2009

Re: Kintex-7 SPI Master Configuration Fail.

so what is your power on reset circuit ?

 

you need to hold off doing anything till after the power is within spec, 

     Your flash clock seems to start way before the power is stable / within specification,

 

can you post the power on reset circuit your using please,

 

 

Posts: 803
Kudos: 151
Solutions: 130
Registered: ‎06-05-2013

Re: Kintex-7 SPI Master Configuration Fail.

Hi,

 

Does it boot from SPI if you toggle program_b after device power ON? Also, Is the JTAG cable connected? 

Are you able to program device using BIT File via JTAG ? 

 

Thanks

Harshit

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