05-16-2018 08:40 AM
I designed a board using Kintex-7 FPGA. Only one of several boards has a configuration fail at boot-up. The power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO. The board with the issue has the following symptoms.
The SPI master signals (cs, clk) are output before the Program_B ramp starts. (VCCO ramp is the same as Program_B.)
I have some questions.
1. When can this issue occur?
2. What is the threshold voltage of the program_b signal?
3. What is the threshold voltage of VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO (2.5V, 3.3V and 1.8V) in power-on sequence to start the power-on reset?
05-16-2018 10:31 AM - edited 05-16-2018 10:32 AM
looks like you have a 50 ms rise time on that prog_b,
Whats your vcc ramp time, does it meet the specs ?
what size pull up do you have , prog_b needs less than 4k7, I'd usually use 1K
05-17-2018 05:03 AM
Thank you for your response.
All VCC ramps are less than 50ms. It seems to satisfy the spec. And the pull-up resistor for prog_b is 4.7 Kohm.
05-17-2018 09:40 AM
so what is your power on reset circuit ?
you need to hold off doing anything till after the power is within spec,
Your flash clock seems to start way before the power is stable / within specification,
can you post the power on reset circuit your using please,