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Visitor tneto
Visitor
1,328 Views
Registered: ‎10-30-2017

Master BPI Configuration Interface

Hello. Both, Xilinx and Micron pointed out MT28EW01GA as the recommended part to be used together, but so far there is no guideline available. Even on latest kits, Xilinx stills promoting an obsolete part. So is there any suggestion or schematic that proofs that this combination really works and/or some statement that addresses the new memory pins "BYTE#" and "RY/BY#"? Thanks.

 

 

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5 Replies
Moderator
Moderator
1,287 Views
Registered: ‎04-12-2017

Re: Master BPI Configuration Interface

Hello @tneto,

 

Yes, its true that some of the Micron flashes are going EOL and there has been call of last purchase from Micron for this flashes.

Are you looking for synchronous BPI flashes ?

For which device you are looking for parallel BPI nor flashes ?

Is there any requirement of fast configuration speeds ?

 

Please answer above questions.

Thank you.

 

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Visitor tneto
Visitor
1,218 Views
Registered: ‎10-30-2017

Re: Master BPI Configuration Interface

Hello @kvasantr. Thanks for looking into my post. The memory I've selected so far is MT28EW01GABA1LPC-0SIT. Asynchronous is acceptable and no special requirement on configuration speed. My concerns are on new pins BYTE# and RY/BY#. Currently pull them up seems okay to me but I'd have your confirmation if they need to be mapped on FPGA or not. If yes please point me the special pins where to connect. Thank you.

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Moderator
Moderator
1,210 Views
Registered: ‎05-02-2017

Re: Master BPI Configuration Interface

hi @tneto,

 

can you please let us know which version of the tool your using and FPGA part number.

 

 

Ta

sekhar

Regards
Chandra sekhar
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Visitor tneto
Visitor
1,203 Views
Registered: ‎10-30-2017

Re: Master BPI Configuration Interface

Hello @csattar. For Vivado I'm currently on 2017.2 but always able to get the most updated one and FPGA part number, XC7VX690T-3FFG1761C. Thank you.

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Visitor andrew3huang
Visitor
582 Views
Registered: ‎09-17-2018

Re: Master BPI Configuration Interface

Hi, Due to EOL of MT28GU01GAAA1EGC-0SIT, we modified our XC7V2000T board to use MT28EW01GABA1LPC-0SIT. Since MT28GU01GAAA1EGC-0SIT is a 16 bit NOR and we also pull up the BYTE# pin of MT28EW01GABA1LPC-0SIT. We connected the same address of MT28EW01GABA1LPC-0SIT as MT28GU01GAAA1EGC-0SIT from XC7V2000T. Connect MT28EW01GABA1LPC-0SIT pin E2(A0) to XC7V2000T pin AH31(IO_L24N_T3_A00_D16_14). After the new FPGA board come back, Vivado is able to erase and program the MT28EW01GABA1LPC-0SIT chip. But it fail on "Boot from Configuration Memory Device". Do we need to connect MT28EW01GABA1LPC-0SIT pin E2(A0) to XC7V2000T pin AG31(O_L24P_T3_A01_D17_14) ? Thanks!! Andrew
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