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Observer hchen213
Observer
8,287 Views
Registered: ‎04-08-2016

Partial Reconfiguration Controller with SPI flash KCU105

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Hello,

 

I am trying to use the PRC with spi flash on KCU105 device. I built everything following the tutorial UG947, except I had to use SPI flash instead of the BPI flash given in the tutorial. I am using the AXI_QUAD_SPI IP instead of AXI_EMC, and I instantiated STARTUPE3 outside of the AXI_QUAD_SPI flash. I set  the AXI_QUAD_SPI into XIP mode. 

 

Bascially, I am trying to load the partial bitstreams from SPI flash into configuration memory through the Partial Reconfiguration Controller IP and the AXI_QUAD_SPI IP. 

 

When I run the program, I can see that the data on m_axi_mem_rdata matches the data in the partial bitstream bin file until a SHUTDOWN packet is written into the Command Register through ICAPE3. In the bitstream file, it shows as (30 00 80 01, 00 00 00 0b). After that, the  data on m_axi_mem_rdata no longer matches the data in the partial bitsream. 

 

By the way, I am running at 100 MHz for my program, and 50 MHz for the SPI Flash.

 

I am wondering what is the correct way of reading the partial bitstreams from spi flash into ICAP? 

 

You can see the EOS(end of startup) goes from 1 to 0 in the picture below.

1.png

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Observer hchen213
Observer
14,695 Views
Registered: ‎04-08-2016

Re: Partial Reconfiguration Controller with SPI flash KCU105

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So I finally figure it out.

 

To disbale to CRC, I had to give "set_property BITSTREAM.GENERAL.CRC DISABLE [current_design]" in the constraint file.

 

To disbale the SHUTDOWN sequence which is embedded in the partial bitstream file, I had to change the bitstream file content "30 00 80 01 00 00 00 0B" to "30 00 80 01 00 00 00 00". So instead of writing the SHUTDOWN command to the configuration memory, and it does nothing. 

 

I hope it help anyone who may be having similar problems

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Observer hchen213
Observer
8,153 Views
Registered: ‎04-08-2016

Re: Partial Reconfiguration Controller with SPI flash KCU105

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I tried to search around the forum more carefully for an answer and it seems my suspicion is confirmed.

 

https://forums.xilinx.com/t5/7-Series-FPGAs/Load-PR-bitstream-from-FLASH-memory-using-ICAP/m-p/665715#M14009

 

It looks like the problem is indeed due to the shutdown packet. The posted solution is to "dissable the integrated CRC and change the comand with two noops".

 

Can anyone elaborate how to disbale the integrated CRC, and do I have to manually change the commands with two noops in the bin file?

 

Any help will be greatly appreciated. 

 

Thanks

 

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Observer hchen213
Observer
14,696 Views
Registered: ‎04-08-2016

Re: Partial Reconfiguration Controller with SPI flash KCU105

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So I finally figure it out.

 

To disbale to CRC, I had to give "set_property BITSTREAM.GENERAL.CRC DISABLE [current_design]" in the constraint file.

 

To disbale the SHUTDOWN sequence which is embedded in the partial bitstream file, I had to change the bitstream file content "30 00 80 01 00 00 00 0B" to "30 00 80 01 00 00 00 00". So instead of writing the SHUTDOWN command to the configuration memory, and it does nothing. 

 

I hope it help anyone who may be having similar problems

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3,831 Views
Registered: ‎04-24-2016

Re: Partial Reconfiguration Controller with SPI flash KCU105

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hello,

sorry, you have a good experience with using AXI quad spi ip core, and your project title may be the same as mine, so i need your help and i want ask you, how did you connect the bidirectional pins of the spi ip core with the flash memory pins in FPGA. flash memory has only six pins as shown in attachments, and the for each port of spi ip core there are 3 pins.

please reply me if you can.

 

thanks in advance

 

Untitled.jpg
Untitled1.jpg
Untitled2.jpg
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1,292 Views
Registered: ‎04-18-2018

Re: Partial Reconfiguration Controller with SPI flash KCU105

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你好,我也在用SPI Flash 存储部分bit流文件,但是我在使用axi_quad_spi控制器时,有几个接口不知道如何连接,不知道能否请教您一下?

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Observer hchen213
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Registered: ‎04-08-2016

Re: Partial Reconfiguration Controller with SPI flash KCU105

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I connect the SPI IP to the STARTUP primitive, STARTUP primitive should only have 1 pin for each flash IO pin instead of 3.
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