06-03-2015 03:33 AM
I'm working on partial reconfiguration for 7-series Zynq for a thesis' project. I'm trying to partial reconfigure a simple up-down counter instantiated on the PL using the ICAP port. I had instantiated the AXI HWICAP core for this scope, and wrote the software that will run on my application.
The main steps are:
1- initially program the FPGA with the count down version of my counter
2- using QSPI driver load into DDR the partial .bin file with the count up version of my counter ( in interrupt mode)
3- select the icap interface using the dcfg driver enabling the icap path
4- initialize the hwicap device in interrupt mode
5- read back the file from the ddr and send it to the Hwicap core
i double checked the contents of the main registers of dcfg and hwicap device and they are correct. Also the configuration file is stored and read correctly. The program runs without error and the hwicap interrupt mode works fine: the handler is called the right number of time and transfer all the words but nothing happen and the PL is not reconfigured. I attach my code.
I use the Vivado 2014.4 and Xilinx SDK 2014.4 tools.
Please Help me!
06-07-2015 09:14 AM - edited 06-07-2015 09:16 AM
Have you gone through this application note in detail?
it explains how to synthesize the bitstream properly and there's a program re-flashing the fpga in an embedded linux context at the very end
11-02-2016 09:46 AM