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240 Views
Registered: ‎09-22-2017

Questions about SEM IP and ICAP

I'm tring to inject error using SEM IP on ZC706 board. I write a FSM to control the inject interface on SEM IP, and set the PCAP_PR and icap_grant signal by zynq.
I set the IP option as follow:
 
无标题.png
 
 
Finally, it seems worked. but when I see the debug wave and the FSM's counter info, I have some questions.
 
1. In SEM's Product Guide, "The inject_strobe signal should be pulsed high for one cycle, synchronous to icap_clk, concurrent with the application of a valid address to the inject_address input." But I find the FSM pulsed this signal high for one cycle many times, the SEM can finally get the command and change the status. This occurs both when input direct state change and inject error at linear frame address commands.
 
2. When SEM recieve an error inject command, the status status_injection assert, Indicates that SEM is injecting an error. I make a counter in my control logic, and find it takes about 250,000 cycles until SEM come back to idle. I wonder if this is correct.
 
3. In PG's port description, the FRAME_ECC interface is marked shade, indicate that FRAME_ECC interface only exist in certain configurations. What's the function of FRAME_ECC in error injection. And can the SEM IP inject error without FRAME_ECC?
 
4. I can only find a few about ICAPE2, in UG953. Are there any further info about ICAP and ICAPE2, like how ICAPE2 manage config mem, or maybe example of ICAPE2.
 
Hope for reply, any suggestions will be helpful
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9 Replies
Xilinx Employee
Xilinx Employee
208 Views
Registered: ‎08-10-2008

回复: Questions about SEM IP and ICAP

Hi,
1. it's expected that inject_strobe toggles when you make state change. Take this signal as an Enable with inject_address works as the command data. If you read pg036 you can see this is the command interface for all kinds of commands, not only for error injection.
2. if you mean it takes that long from status_injection to IDLE, that's quite long. Do you enable the Mon interface? Make sure there is no throttling. And monitor all status_* signals. Tell me how each changes during this phase.
3/4. FRAME_ECC and ICAP are must for SEM IP to work. I will suggest you not dig into them, especially FRAME_ECC.

If you want to learn about ICAP, you can take a look at UG470 and xapp733. In a short, take ICAP as an internal mirror of the SelectMAP configuration interface. It can accept almost all configuration commands from logic. It's used not only in SEM but also MultiBoot, Partial, etc.

Ivy
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192 Views
Registered: ‎09-22-2017

Re: Questions about SEM IP and ICAP

Thanks for your reply.

 

1. I know that the inject interface is like a command interface for all kinds of command. In my test, I try two kinds of command, direct state change and inject error at linear frame address. But it seems SEM do not respond the command at once, or it takes a few cycle for SEM to process the command? See the screenshot of debug waveform below.

idle2inject.pnginject an errorobservation2idle.pngobservation to idle

 

In the waveform, sem_status is the status interface, I assigned the signal like this, so 0x00 stands for the idle state, 0x20 for the observation state, and 0x04 for the injection state.

assign sem_status = { status_heartbeat,
                      status_initialization,
                      status_observation,
                      status_correction,
                      status_classification,
                      status_injection,
                      status_essential,
                      status_uncorrectable };

 

 

2. It takes a long time from status_injection to IDLE, so I can't catch it on the waveform. I read the status change through Zynq's GPIO, and print on putty. I also read the FSM's counter, here is the screenshot. 

无标题2.png

 I think there must be something wrong to take such a long time.

It seems the monitor interface can't be disabled. I kept the mon sub-module from the example design, and left the external UART interface (monitor_tx & monitor_rx) unconnected. Does this affect the behavior?

 

 

 

 

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147 Views
Registered: ‎09-22-2017

Re: Questions about SEM IP and ICAP

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Xilinx Employee
Xilinx Employee
141 Views
Registered: ‎08-10-2008

Re: Questions about SEM IP and ICAP

Checking your first screenshot:

why inject_strobe be active for so many times? It should be positive for ONLY one cycle when there is a valid inject_address on the data ports. And wait until the command is active and finished, you can issue the next command (valid inject_address & one cycle inject_strobe). 

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130 Views
Registered: ‎09-22-2017

Re: Questions about SEM IP and ICAP

@iguoThanks for reply. At first, I asserted the inject_strobe for only once. But it seemed the SEM not respond the command, and still remain the current status. Then I change my design to this, I assert the command until it the SEM change state. Should I assert the strobe for one cycle and just wait for SEM's response?

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Xilinx Employee
Xilinx Employee
121 Views
Registered: ‎08-10-2008

Re: Questions about SEM IP and ICAP

Exactly. Wait for the response. SEM IP does not accept successive injections.
If for one single injection you don't see any response, the timing or instantiation of the IP may get some issues. You can use the pure example design, inject via ILA and VIO, and then monitor how each signals toggles. Modify your own code in case needed.
------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------
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113 Views
Registered: ‎09-22-2017

Re: Questions about SEM IP and ICAP

@iguoI modified my control logic to send only one strobe. Still, it took a long time for SEM to change from injection state to idle state. I ask my friend who is using ICAP, it usually takes about hundred cycles by using ICAP. Why does the SEM take a long time, is that correct ?

 

无标题.png

 

The inject commands which I asserted are:

0xC000001021
0xC00666BC9F
0xC00324A91D
0xC001A3F15C
0xC000000000
0xC000001021

time use: 

putty_2.png

 

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Xilinx Employee
Xilinx Employee
79 Views
Registered: ‎08-10-2008

Re: Questions about SEM IP and ICAP

I don't remember how long it would take but it should not be so long.

Measure the time taking of an example design and compare it with your own code.

Make clear the following items:

1. how fast is your icap_clk;

2. how fast is your measure clock;

3. capture the mon logs.

------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------
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33 Views
Registered: ‎09-22-2017

Re: Questions about SEM IP and ICAP

@iguo

I failed to run the example design because I only have a Zynq board. It seems the example design is for PL only devices.

 

The icap_clk and the measure clock are both 50MHz. I can only get the output of status interface, and I didn't use the MON interface so I can't get the MON log.

 

I'll try to control ICAP instead. Thanks for your reply.

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