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Visitor pier-yves
Visitor
9,518 Views
Registered: ‎09-16-2014

Spartan6 serial configuration

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Hello,

I am working on a design including a CPU with SPI capability and a Spartan6 FPGA. I'd like to be able to configure the FPGA with my CPU.   According to this document, Spartan 6 offer the Slave Serial configuration which seems to meet my needs.

 

The thing that bothers me is the timing of that serial protocol. I'd like to use a standard peripheral (such as SPI) to send a bitstream. The timing says that I must pull down PROGRAM_B, wait for INIT_B to go down and up and then sends the data. This handshakes seems to me kind of hard to implement with SPI. Here's the solution I could see

 

  • Bit bang PROGRAM_B & INIT_B then sends the data over an SPI bus. 

This would probably be one of the most elegant way to do it. Main issue is that I can't share my SPI bus with other device since there is no ChipSelect feature on the Spartan6 for serial configuration. I could maybe add a tri-state buffer on the SPI clock controlled by a CSn line ? 

 

  • Completely bit bang the data transfer.

Seems like an ugly solution to me but still has the advantage of not taking a complete SPI bus or too many data line.

 

  • Make my CPU act like a slave SPI device and trigger the configuration with PROGRAM_B
  • Having an onboard SPI flash that I can write while my FPGA is in reset state.

What are your thoughts ? I am not stuck here, but none of my solution seems completely appropriate and I am lacking a little bit of experience on this.   

 

What would be your way to configure a Spartan6 with a CPU running Linux ?

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Historian
Historian
17,018 Views
Registered: ‎02-25-2008

Re: Spartan6 serial configuration

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@pier-yves wrote:

 

What would be your way to configure a Spartan6 with a CPU running Linux ?


I think whether the CPU is running Linux or another OS isn't really interesting. I've configured FPGAs from micros, albeit not one that runs an OS. Running an OS likely involves writing a driver for the hardware. That's beyond what I care to do.

 

You are right that since the configuration port doesn't have a chip select input you can't reasonably share the SPI port with other peripherals. Gating the clock might be a solution. 

 

Does the CPU have other synchronous serial ports? A lot of the ARMs have several USARTs which can run in an SPI mode. Use that.

 

As for managing PROGRAM_B and INIT_B, you need two processor I/O port bits for them. PROGRAM_B can be an output. INIT_B should be an input (with a pullup) because you need to monitor its assertion and deassertion before you start shifting out and you need to monitor it while shifting because it's what signals the CRC fail. (Perhaps use an interrupt-capable I/O pin?)

 

You actually need a third bit, because you want to monitor the DONE flag.

----------------------------Yes, I do this for a living.
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Explorer
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Registered: ‎08-19-2014

Re: Spartan6 serial configuration

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If your design is starting from scratch and you don't have any special requirements on the CPU, the I would highly recomend you design this CPU+FPGA combination with a Zynq part instead of a Spartan 6.  There's so much to help you along and building Linux for the Zynq is simple.  However, if you wish to say with your current design setup, then I would consider an approach where you use an external interrupt to watch when INIT_B goes high.  If your CPU has some GPIO, you could use them instead.  If you won't be performing any reconfiguration of the FPGA during runtime, you could simply use a power on reset circuit with adjustable delay to hold PROG_B low as your CPU boots and then gets t a point where it is waiting for INIT_B to interrupt.  After the set time, the power on reset circuit will release PROG_B and INIT_B will go high afterwards, at which point you'll know you're ready to configure the FPGA.  Another option could be to add a very small CPLD to your design to aid in this configuration system.

 

-Jordan

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Historian
Historian
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Registered: ‎02-25-2008

Re: Spartan6 serial configuration

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@jordanki_bah wrote:

If your design is starting from scratch and you don't have any special requirements on the CPU, the I would highly recomend you design this CPU+FPGA combination with a Zynq part instead of a Spartan 6.  


He may already have a processor selected and tools purchased and perhaps even the application already running on the processor. So moving to Zynq requires learning a whole new toolkit.

 

Plus, I would imagine that his separate CPU /FPGA solution is one helluva lot cheaper than the Zync proposition.

----------------------------Yes, I do this for a living.
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Historian
Historian
17,019 Views
Registered: ‎02-25-2008

Re: Spartan6 serial configuration

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@pier-yves wrote:

 

What would be your way to configure a Spartan6 with a CPU running Linux ?


I think whether the CPU is running Linux or another OS isn't really interesting. I've configured FPGAs from micros, albeit not one that runs an OS. Running an OS likely involves writing a driver for the hardware. That's beyond what I care to do.

 

You are right that since the configuration port doesn't have a chip select input you can't reasonably share the SPI port with other peripherals. Gating the clock might be a solution. 

 

Does the CPU have other synchronous serial ports? A lot of the ARMs have several USARTs which can run in an SPI mode. Use that.

 

As for managing PROGRAM_B and INIT_B, you need two processor I/O port bits for them. PROGRAM_B can be an output. INIT_B should be an input (with a pullup) because you need to monitor its assertion and deassertion before you start shifting out and you need to monitor it while shifting because it's what signals the CRC fail. (Perhaps use an interrupt-capable I/O pin?)

 

You actually need a third bit, because you want to monitor the DONE flag.

----------------------------Yes, I do this for a living.
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Visitor pier-yves
Visitor
9,469 Views
Registered: ‎09-16-2014

Re: Spartan6 serial configuration

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Thank you very much for your comments. 

I think I will go with GPIOs on PROGRAM_B and INIT_B and dedicate a full SPI line to the FPGA programming. I do have more than one.

 

Very appreciated.

 

 

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Explorer
Explorer
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Registered: ‎08-19-2014

Re: Spartan6 serial configuration

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@bassman59 wrote:

... I would imagine that his separate CPU /FPGA solution is one helluva lot cheaper than the Zync proposition.


In the case of a production run of hundreds, I would say it's possible to be a wash on cost.  For example, if one selects the lowest speed grade Zynq 7010 in the CLG225 package, Avnet says they're just over $50 each.  A comprable Spartan 6 (logic cell wise) could be the LX25 N3 speed grade in the 256FCBGA package (I'm making several assumptions on needed pins and logic cells), which Avnet wants $32 each.  If the microprocessor costs $10, and the additional board space and microprocessor support compontents cost another $4 (excluding SDRAM and Flash memory), the delta is $4 per board.  If the Zynq can give a $4 per board advantage through the ease of development, then it's a break even situation.  However, if the ease of development greatly reduces development labor costs to where more than $4 per board is saved, then there's a possible advantage with the Zynq.

 

-Jordan

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