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Tandem PROM - Need help

Posts: 29
Registered: ‎11-26-2016

Tandem PROM - Need help



I successfully generated a tandem PROM bitstream.

When the kintex ultrascale device is configured straight from Vivado with it, everything works fine.

Also when the tandem bitstream is separated in Stage 1 and Stage 2 using:


set_property HD.TANDEM_BITSTREAMS SEPARATE [current_design]


the workflow "Load Stage 1 -> Reboot -> Load Stage 2 -> Use Design" works fine.


However, loading it from an external n25q256 flash does not work. It seems like only the Stage 1 is loaded, because loading Stage 2 during runtime makes everything work again.
The hardware (and configurations) is ok i guess, since the PROM FPAG configuration process works fine when tandem is deactivated and the XDC is basically the same (except for the CONFIG_MODE parameter):


set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE {SPIx4} [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]


The mode pins are set to SPI-Mode. Stage 1 contains Bank 0 and 65. sys_reset is configured to use a pullup.

The MCAP interface is disabled and the mcap_design_switch unused. ICAP is also not used.


cap_gnt <= '0';
cap_rel <= '1';


How I generate the bin file


write_cfgmem -force -format bin -size 32 -interface SPIx4 -loadbit "up 0x0 input.bit" output.bin


After "Boot from Configuration Memory Device" + Reboot of the System




 It seems like something is stopping the Stage 2 stream from beeing successfully loaded. Or could it be a reset problem?

Hope somebody can point me in the right direction,



Posts: 1,290
Registered: ‎01-15-2008

Re: Tandem PROM - Need help

tandem prom with spi is having an issue in 2016.4 vivado. This is fixed in 2017.1 which is released


Posts: 29
Registered: ‎11-26-2016

Re: Tandem PROM - Need help

Hmm, even now that I know, I cannot seem to find any report about this issue and it is also not listed in 2017.1 resolved issus. 
Can you please post the source.



Posts: 29
Registered: ‎11-26-2016

Re: Tandem PROM - Need help

The problem persists for me, even after an upgrade to Vivado 2017.1.


For testing purposes, I enabled the MCAP interface to load Stage 2 from the Host using the Xilinx MCAP Driver for Windows. Everything works as expected after setting the MCAP_Design_Switch to 1.

The exact same design built without the properties below to split the bitstream stages does not work.


set_property HD.OVERRIDE_PERSIST FALSE [current_design]
set_property HD.TANDEM_BITSTREAMS Separate [current_design]

The stage 2 has a VIO core, which is not detected over JTAG after the config PROM bootup.

The MCAP_Design_Switch in the "MCAP Control Register" in the Vendor-Specific Extended Capabilities Register of the PCIe Core is also not set to '1' after the boot, as it should according to https://www.xilinx.com/Attachment/Xilinx_Answer_64761__UltraScale_Devices.pdf

Setting it manually crashes the host on the next PCIe access operation.


It seems again like Tandem PROM only loads Stage 1, but not Stage 2!


Does anybody use Vivado 2017.1 for Tandem PROM successfully?

Any Ideas how to resolve the issue?

Posts: 29
Registered: ‎11-26-2016

Re: Tandem PROM - Need help

In order to reproduze the issue, I used the PCIe Example Design with external STARTUP primitive.


  STARTUPE3 startup_i (
    .CFGCLK(),          // output
    .CFGMCLK(),         // output
    .DI(),              // output
    .EOS(eos),          // output
    .PREQ(),            // output
    .DO({4'b000, probe}),       // input
    .DTS(4'b0000),      // input
    .FCSBO(1'b0),       // input
    .FCSBTS(1'b0),      // input
    .GSR(1'b0),         // input
    .GTS(1'b0),         // input
    .KEYCLEARB(1'b1),   // input
    .PACK(1'b0),        // input
    .USRCCLKO(1'b0),    // input
    .USRCCLKTS(1'b0),   // input
    .USRDONEO(1'b1),    // input
    .USRDONETS(1'b0)    // input

The wire "eos" is connected to the eos input of the PCIe Core, "probe" is connected to a VIO (which is placed in Stage2) and set to a constant value:


`ifdef EN_ILA 
    ila_0 ila_0_1 (

assign probe = 1'b1;

When EN_ILA is NOT defined, the Stage 2 is loaded as it sould (Verified by the Configure MCAP Design Switch Bit in PCIe Registers).


However, when EN_ILA is defined, Stage 2 loading fails!

Posts: 29
Registered: ‎11-26-2016

Re: Tandem PROM - Need help

I added the archived modified PCIe Tandem PROM example Design I mentioned above (Vivado 2017.1).
Maybe somebody can figure out what causes the issue.


Thank you in advance.

Posts: 14
Registered: ‎05-22-2008

Re: Tandem PROM - Need help

I have exactly the same issue as described above, using 2017.1


Loading the Tandem PROM file from SPI flash fails, loading it through JTAG seems to work. The done pin does not get asserted but I can see the Stage1 works.


Loading regular bitfiles through SPI also works if we use EMC CLK. It does not without EMC CLK. This kind of suggests not enough programming clocks given by the FPGA to load the SPI files, but I can't seem to find a setting to select this.


What can I do to make Tandem PROM work? Is it an issue that is resolved in 2017.2?