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Observer veratis_0310
Observer
347 Views
Registered: ‎07-18-2018

[VCU-118] Big PR logic for ICAP

Our team is using PCI-E to put encrypted bitstream into the FPGA, and decrypt it. Then, put it in ICAP. But ICAP's FIFO's length is only 1024, and it's too small for our partial bitstream. Is there any solution to this? (Like fixing fifo parameter in ICAP IP)
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Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎06-06-2018

Re: [VCU-118] Big PR logic for ICAP

Hi @veratis_0310,

 

Please refer this link https://www.xilinx.com/Attachment/Xilinx_Answer_64761_Ultrascale_Devices_v8.pdf , helpfull for your query.

 

Regards,

Deepak D N

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