UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
428 Views
Registered: ‎03-11-2019

Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hello,

I am using an Artix-7 FPGA (XC7A100T-3FGG484) & (XC7A200T). Also, we use one XCF032P PROM chip for loading our (.mcs) file. It seems to successfully load a large (.mcs) file, as DONE signal is active and FPGA functions seem to work. When I upload a small (.bit) & (.ltx) file with very low utilization like a simple counter, programming is successful and Chipscope can be used. However, when trying to upload a much bigger (.bit) & (.ltx) file through Hardware Manager on Vivado 2016 & 2017, this message shows up:

ERROR: [Labtools 27-3165] End of startup status: LOW

I took a look at the CONFIG_STATUS & BOOT_STATUS Registers (after programming) and this is what I get:

CONFIG_STATUS.PNGBOOT_STATUS.PNG

0 Kudos
17 Replies
Xilinx Employee
Xilinx Employee
386 Views
Registered: ‎03-07-2018

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hello @david_diaz_mxi 

Try reducing cable speed of programming cable in Vivado Hardware Manager and try configuring your FPGA.

 

 

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
0 Kudos
372 Views
Registered: ‎03-11-2019

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hello @bpatil

We have reduced the cable speed to 750 kHz and still get the same error.

Regards,

David

 

0 Kudos
Moderator
Moderator
354 Views
Registered: ‎06-05-2013

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hi David,

Can you share the report_property -all [current_design] outcome after opening the bigger implemented design.
https://www.xilinx.com/support/answers/54073.html

Since the status valid in the right snapshot of status register is 0 so I am not sure what may be wrong. Try to use refresh HW device before sharing the status registers.

How many boards show this kind of failure?

Thanks
Harshit
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
339 Views
Registered: ‎03-11-2019

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hi @harshit 

So we have 3 different designs, 1 using the XC7A100T & 2 using the XC7A200T. They all display the same error when trying to upload large (.bit) & (.ltx) files.

So per your suggestion, I refreshed HW device and got these STATUS Registers:

Regards,

David

Moderator
Moderator
330 Views
Registered: ‎06-05-2013

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hi David,
Thanks for the status registers. I can see a CRC error in the status registers. Bit05_0_CRC error and BIT00_CRC error are set.

Here are the more details on status registers https://www.xilinx.com/support/answers/34909.html

You can also try to load the same bit after disabling the CRC check. See if it get loaded.
BITSTREAM.GENERAL.CRC Disable

Regenerate the bit file if possible and look for possible SI issues in JTAG header.
Also try to set the mode pins to some other BPI or SPI mode. Currently these are set to JTAG mode.

Thanks
Harshit
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
311 Views
Registered: ‎03-11-2019

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

@harshit 

We tried shortening the Xilinx JTAG signals (on the cable) as much as possible to minimize any SI issues. We still get the CRC error. We were also able to load the bit file using the (BITSTREAM.GENERAL.CRC Disable) function. However, it did not allow our Chipscope to work. It did not recognize the Debug tool.

What mode pins for BPI or SPI mode should I set to? Are you referring to the M0, M1, M2 configuration?

David

 

0 Kudos
Xilinx Employee
Xilinx Employee
296 Views
Registered: ‎03-07-2018

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hello @david_diaz_mxi 

I believe you are configuring FPGA through JTAG, so mode pin set to JTAG mode is fine.

For configuration, 7 series devices require power on the VCCO_0, VCCO_14, VCCO_15, VCCAUX, VCCBRAM, and VCCINT pins. I have doubt that while configuration one of these power rail having sudden power drop issue and this is causing failure in configuration.

I will recommend to monitor these power rails while configuration of FPGA. 

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Observer ting_mx
Observer
269 Views
Registered: ‎12-27-2017

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hi @bpatil

Thanks for your advice! We will check those power pins.

Meanwhile, is there any posibility that on-board noise interfere the JTAG clock and data signal ? (even the connector and cable no SI issue)

 

Thank you!

 

Ting 

0 Kudos
Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎03-07-2018

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hello @ting_mx 

It is possible for that you can probe JTAG signals near to FPGA and check. Check for working as well as for failing conditions.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Observer ting_mx
Observer
230 Views
Registered: ‎12-27-2017

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

@bpatil 

Thank you!

We have checked the power pins: there is little voltage drop around 50mv. Is it acceptable?

We also check the TDI, TCK at connector side and FPGA input pins , both signals are very clean.

I think there maybe some timing violation.

Since we failed in slow speed programming , I think this is not setup violation, hold-time violation is possible.

My question is how can vivado/hardware manager/debugger  ensure that there is no holdtime violation between TDI and TCK? 

 

Thank you!

 

Ting

 

 

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
220 Views
Registered: ‎03-07-2018

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?


Hello @ting_mx 

 

We have checked the power pins: there is little voltage drop around 50mv. Is it acceptable?

> Kindly check datasheet for recommended voltage range.

We also check the TDI, TCK at connector side and FPGA input pins , both signals are very clean.

I think there maybe some timing violation.

Since we failed in slow speed programming , I think this is not setup violation, hold-time violation is possible.

My question is how can vivado/hardware manager/debugger  ensure that there is no holdtime violation between TDI and TCK? 

> Try performing IDCODE looping (N = 10000) test suggested at https://www.xilinx.com/support/answers/66798.html 

Check https://www.xilinx.com/support/answers/8902.html for detailed understanding of this test.

 


Did you tested your larger design on any other board?

Did you modified mcs or bitstream?

In your case, does FPGA fails to get configured from JTAG as well as flash? Are you able to program flash through JTAG?

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------------------------
Observer ting_mx
Observer
207 Views
Registered: ‎12-27-2017

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hi @bpatil 

Thanks for your quick response.

The datasheet min value is 0.95 max is 1.05, so I think it is still in the working condition.

I can not access the first link , you give to me

 https://www.xilinx.com/support/answers/66798.html 

Yes, I will try this kind of test later, thank you!

But I still have this question: 

How can vivado/hardware manager/debugger  ensure that there is no setup/ holdtime violation between TDI and TCK? 

In timing report, there is no such kind of checking, in our constrain  xdc there is no input delay for those two pins, in PCB guideline there is no trace length reqirement for those pins...

 

Thank you!

 

Ting

0 Kudos
Observer ting_mx
Observer
202 Views
Registered: ‎12-27-2017

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

>In your case, does FPGA fails to get configured from JTAG as well as flash? Are you able to program flash through JTAG?

It is interesting, looks like FPGA can be configured by our on board PROM through impact.

But we want chipscope , is there any way we can use mcs file + *.ltx file? How could we progamming ltx through impact?

Thank you again!

 

Ting

 

0 Kudos
146 Views
Registered: ‎03-11-2019

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Hi @bpatil 

After running the IDCODE looping (N=10000), this was our result:

idcode_loop 10000 0
LOOP Test Finished!
The device is xc7a100t_0
IDCODE is 00000011011000110001000010010011

So does this mean there is no timing violation for TDI/TCK?

Regards,

David

0 Kudos
136 Views
Registered: ‎03-11-2019

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

Also after running the IDCODE looping script, we are able to get a different IDCODE. This different IDCODE seems like it allows us to program large (.bit) files. However, we still cannot get the (.ltx) Chipscope file to work. Here is the following log from the Hardware Monitor:

idcode_loop 10000 0
LOOP Test Finished!
The device is xc7a100t_0
IDCODE is 00010011011000110001000010010011
set_property PROBES.FILE {C:/Users/Jack/Desktop/ARTIX7/R0_190311_XDC/debug_nets.ltx} [lindex [get_hw_devices] 0]
set_property PROGRAM.FILE {C:/Users/Jack/Desktop/ARTIX7/R0_190311_XDC/mx300e_xpro_top.bit} [lindex [get_hw_devices] 0]
program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 896.449 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices] 0]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7a100t_0 and the probes file C:/Users/Jack/Desktop/ARTIX7/R0_190311_XDC/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.

 

Regards,

David

0 Kudos
Adventurer
Adventurer
128 Views
Registered: ‎12-11-2017

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

If there's no clock running to the debug core the ILAs will not load (Vivado will skip them.) Make sure you have a debug clock, and you have included in your constraints.

Example:

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]

Adventurer
Adventurer
125 Views
Registered: ‎12-11-2017

Re: Why am I getting ERROR: [Labtools 27-3165] End of startup status: LOW?

The other error is a signal integrity problem, or noise coupling onto JTAG. For example, if you have a high-current DC-DC regulator on your board the coil can make a strong enough flux that it will mess with JTAG if the signals are close.

0 Kudos