UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
145 Views
Registered: ‎10-01-2010

XAPP1280 (UltraScale SPI Flash access) differences in IP Integrator ports between reference and user design

I am trying to generate a SPI-to-STARTUPE3 interface in IP Integrator based on XAPP1280. The reference design in that app note has a BD Tcl file with the following commands relating to the AXI Quad SPI controller:

set spi_rtl [ create_bd_intf_port -mode Master \
-vlnv xilinx.com:interface:spi_rtl:1.0 spi_rtl ]
set axi_quad_spi_0 [ create_bd_cell -type ip \
-vlnv xilinx.com:ip:axi_quad_spi axi_quad_spi_0 ]
set_property -dict [ list \
CONFIG.C_FIFO_DEPTH {256} \
CONFIG.C_SPI_MEMORY {2} \
CONFIG.C_SPI_MEM_ADDR_BITS {24} \
CONFIG.C_SPI_MODE {2} \
CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} \
CONFIG.C_USE_STARTUP {1} \
CONFIG.C_XIP_MODE {0} \
] $axi_quad_spi_0

connect_bd_intf_net -intf_net axi_quad_spi_0_SPI_0 \
[get_bd_intf_ports spi_rtl] [get_bd_intf_pins axi_quad_spi_0/SPI_0]


My version of the BD Tcl is practically identical save for port and instance names, plus an explicit version number for axi_quad_spi:

set FLASH [ create_bd_intf_port -mode Master \
-vlnv xilinx.com:interface:spi_rtl:1.0 FLASH ] set axi_quad_spi_flash [ create_bd_cell -type ip \
-vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_flash ] set_property -dict [ list \ CONFIG.C_FIFO_DEPTH {256} \ CONFIG.C_SCK_RATIO {2} \ CONFIG.C_SPI_MEMORY {2} \ CONFIG.C_SPI_MEM_ADDR_BITS {24} \ CONFIG.C_SPI_MODE {2} \ CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} \ CONFIG.C_USE_STARTUP {1} \ CONFIG.C_XIP_MODE {0} \ ] $axi_quad_spi_flash connect_bd_intf_net -intf_net axi_quad_spi_flash_SPI_0 \
[get_bd_intf_ports FLASH] [get_bd_intf_pins axi_quad_spi_flash/SPI_0]


The reference design's design_1_wrapper.vhd file has STARTUPE3 instantiated but it is not instantiated in my wrapper file, so it is up to me to add it to the top-level RTL. What would explain this? The differences between the user and reference designs are:

  • Vivado 2018.3 vs. 2016.1
  • VU13P vs. KU040
  • Verilog vs. VHDL
  • Port and instance names

Thanks for your help!

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
89 Views
Registered: ‎08-10-2008

回复: XAPP1280 (UltraScale SPI Flash access) differences in IP Integrator ports between reference and user design

Hi,

Correct me if I misunderstand your question: in most of Xilinx IPs there is always an option that whether or not you want to include a hardware primitive into the IP or not. 

For both, the primitive must be added into the design of course, but you can either have it explictly in the top level wrapper connecting to the IP, or have it included in the IP, shown as part of the IP. There is no difference between the two. Just that if the primitive is external, it's convenient for you to check the connection, or add ILA for monitoring, etc.

------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------
0 Kudos