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Observer nate.wang
Observer
107 Views
Registered: ‎03-04-2013

got error "[Labtools 27-3165] End of startup status : LOW" during configuration

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Hi Sir,

I designed a small PCB which daisy chained total 5 JTAG devices for FPGA configuration, schematic as below :

JTAG_sch.png

 

On the above schematic U1 is the JTAG programing module from DIGILENT (https://store.digilentinc.com/jtag-smt2-surface-mount-programming-module/), J2/3/4/5/6 is the JTAG connectors that connect to different FPGA boards.

By using this PCB all the FPGA devices can be recognized through JTAG as below :

(for simplicity, TDI and TDO signal of J4 are shorted so only 4 FPGA devices are connected)

recog.png

 

However, if I try to perform configuration I got the error as below :

15MHz_TCK_series_BLM18AG121SN1-TDI-TDO-TCK3V3_series_BLM18AG121SN1_error.png

I do noticed that there is signal integrity problem on the PCB (https://forums.xilinx.com/t5/Other-FPGA-Architectures/Labtools-27-3165-End-of-startup-status-LOW/td-p/731668), for example, there are glitches on the TCK signal waveform at default 15MHz configuration clock :

15MHz_TCK.png

After various trials of impedance tuning, I decided to add EMI beads on the TCK signal, then got waveforms for J2/J3/J5/J6 as below (yellow : TCK / green : TDI / blue : TDO)

  • J2

15MHz_TCK_series_BLM18AG121SN1-TDI-TDO-TCK3V3_series_BLM18AG121SN1_J2.png

  • J3

15MHz_TCK_series_BLM18AG121SN1-TDI-TDO-TCK3V3_series_BLM18AG121SN1_J3.png

  • J5

15MHz_TCK_series_BLM18AG121SN1-TDI-TDO-TCK3V3_series_BLM18AG121SN1_J5.png

  • J6

15MHz_TCK_series_BLM18AG121SN1-TDI-TDO-TCK3V3_series_BLM18AG121SN1_J6.png

 

To my understanding, if at the rising edge of TCK signal the high/low voltage level of TDI/TDO signals is clear, TDI signal should be able to be correctly clocked into FPGA and TDO signal should also be correct in this case, and on the above scope measurements I believe the requirement is fulfilled, am I correct ?

However, I still got the error "[Labtools 27-3165] End of startup status : LOW" during configuration, any suggestion would be very appreciated, thansk.

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1 Solution

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Observer nate.wang
Observer
49 Views
Registered: ‎03-04-2013

Re: got error "[Labtools 27-3165] End of startup status : LOW" during configuration

Jump to solution

Hi Xilinxacct,

Sorry I just found a mistake in my schematic, voltage level of J2/J3 should be 3.3V not 2.5V, after fixing this issue, JTAG configuration works much more normally but I still met some problem, I will close this post and issue a new post for help, thanks.

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3 Replies
Observer nate.wang
Observer
84 Views
Registered: ‎03-04-2013

Re: got error "[Labtools 27-3165] End of startup status : LOW" during configuration

Jump to solution

Hi Xilinxacct,

Thanks for the reply, but could you explain more about "Root cause of the issue was the clock driving some of the fpga logic including an ILA for debug was missing" ? What should I do to check whether if there is missing clock or not ? 

 

Thanks.

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Observer nate.wang
Observer
50 Views
Registered: ‎03-04-2013

Re: got error "[Labtools 27-3165] End of startup status : LOW" during configuration

Jump to solution

Hi Xilinxacct,

Sorry I just found a mistake in my schematic, voltage level of J2/J3 should be 3.3V not 2.5V, after fixing this issue, JTAG configuration works much more normally but I still met some problem, I will close this post and issue a new post for help, thanks.

0 Kudos