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Participant bbertrand
Participant
170 Views
Registered: ‎01-24-2011

quad spi flash configuration and SEM on FPGA KU060

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Hello,

I had several question on kintex utltrascale (xcku060),

what is the benefit of using dual quad spi flash configuration against using only one quad spi flash configuration?

Can we use the Soft Error Mitigation with external quad spi flash configuration?

Thanks,

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1 Solution

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Participant bbertrand
Participant
95 Views
Registered: ‎01-24-2011

Re: quad spi flash configuration and SEM on FPGA KU060

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Hello,

I find some answer about my question in https://www.xilinx.com/support/answers/39285.html

https://www.xilinx.com/support/answers/39285.html

"The SPI memory used for the SEM IP is independent of the configuration bitstream storage.

This means that an additional SPI flash specifically for the use of the SEM IP is needed.

The SPI flash is interfaced to the SEM IP through four user I/O pins."

Then on our xcku board we need one configuration flash and one flash for the SEM.

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3 Replies
Participant bbertrand
Participant
137 Views
Registered: ‎01-24-2011

Re: quad spi flash configuration and SEM on FPGA KU060

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Hello,

I read and re-read xilinx document on SEM IP Soft Error Mitigation,

In the SEM IP the spi flash helper block provides an interface between the SEM IP and the external strorage(FLASH).,

but i dont know if i can use the spi flash helper block in external SPI1x or SPI4x?

Someone can help on this aerospace application ro

where can I find support/contact about this  aerospace application.

Thanks

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Xilinx Employee
Xilinx Employee
119 Views
Registered: ‎03-07-2018

Re: quad spi flash configuration and SEM on FPGA KU060

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Hello @bbertrand

I believe you are planning to use XQRKU060 space grade FPGA.

I will recommend file SR for your issue for getting information for your query.

Check https://www.xilinx.com/support/answers/64454.html for more details.

Regards,
Bhushan

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Participant bbertrand
Participant
96 Views
Registered: ‎01-24-2011

Re: quad spi flash configuration and SEM on FPGA KU060

Jump to solution

Hello,

I find some answer about my question in https://www.xilinx.com/support/answers/39285.html

https://www.xilinx.com/support/answers/39285.html

"The SPI memory used for the SEM IP is independent of the configuration bitstream storage.

This means that an additional SPI flash specifically for the use of the SEM IP is needed.

The SPI flash is interfaced to the SEM IP through four user I/O pins."

Then on our xcku board we need one configuration flash and one flash for the SEM.

0 Kudos