08-20-2014 02:08 AM
I want to read back the configuration frames from XC5VFX130 FPGA through an internal port and compare them with that stored in radiation-hardened memory to detect and correct SEUs. I have read the ‘Virtex-5 FPGA Configuration User Guide’ (UG191) and these are my questions:
Question one: From a configuration point of view, I draw the virtex-5 FPGA fabric according to the figure6-11 and figure6-12 in UG191（page 131,132 in UG191）.
The virtex-5 FPGA fabric drew by myself is shown in fig.1.
Fig.1 virtex-5FPGA fabric
Is it correct? I think it is wrong. Because it’s described in the UG191 that a row consists of a stack of basic blocks (20 CLBs, 40 IOBs, 4 block RAMs, etc.)(page 129 in UG191).
But a row only have 2CLBs,2IOBs,3block RAMs,1DSP in figure6-12(page 132 in UG191).I don’t know why, and I want to know the complete structure of a row.
Question two:It’s described in the UG191 that the largest Virtex-5 device has a total of 12 rows(6 in each half).But my device is XC5VFX130 FPGA and I want to know how many rows in each half.
this is the link of UG191:http://www.xilinx.com/support/documentation/user_guides/ug191.pdf
Thanks in advance:)
07-05-2017 01:12 AM
08-01-2017 07:55 PM