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Contributor
Contributor
6,346 Views
Registered: ‎06-03-2011

Accounting for Latency, how ?

Hello

 

I’m working with AccelDSP 11.1 and I plan to perform a HW Co-Sim on my board,

 

In the final step (Verify HW Co-Sim) of HW Co-Sim design flow, and exactly in the “Verify HW Co-Simulation Report”, I had the following sentence:

 

The latency of your design is greater than the number of clock cycles.

You will need to account for this when using your scriptfile.

 

So I want to know:

          How does it mean by “latency” in this case or design flow?

          How can I do the required accounting?

____

Regards

Sofiene

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12 Replies
Advisor eilert
Advisor
6,339 Views
Registered: ‎08-14-2007

Re: Accounting for Latency, how ?

Hi Sofiene,

it seems as if you have specified some number of clock cycles for simulation.

But if the latency (which is basically the number of pipelined registers)

in your design is greater than the simulation clock cycles, you will see no output at all.

 

So, the minimum number of clock cycles for a simulation is

  NumberOfTrueInputSamples+Latency

 

Have a nice simulation

  Eilert

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Contributor
Contributor
6,312 Views
Registered: ‎06-03-2011

Re: Accounting for Latency, how ?

 

Hello ,

 

Thank you for responding,

 

I haven't specified any number of clock cycles for my co-simulation, even I don't know how to do it,

 

I had the cited sentence in the “Verify HW Co-Simulation Report” and in the same time and had a successful co-simulation with the desired results !

 

So if you tell me how to specify this parameter (the number of clock cycles for the simulation) when it is necessary, and how can I know the latency or estimate it ?

 

____

Regards

Sofiene

 

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Advisor eilert
Advisor
6,306 Views
Registered: ‎08-14-2007

Re: Accounting for Latency, how ?

Hi Sofiene,

since you are working with Accel-DSP it's not so easy to find out about the latency of your design.

Instead you should already know it when writing your code, since this goes hand in hand. Designing the algorithm includes calculation of latencies and then you start coding.

 

Now let's assume you know the latency, or have at least some idea of the order of magnitude.

You also know the simulation period, set in the System Generator block.

So, in the Simulink Simulation Parameters dialog, you find the Simulation stop time.

The parameter should be greater than:

simulation_period * (latency + length(Input_data_vector) + some_extra_time)

 

If you have defined these values in your workspace, you can put the formula in the parameter field, and will always have a sufficiently long simulation time.

 

You wrote "and had a successful co-simulation with the desired results".

This may be, when the number of input data is greater than the latency of your design.

Have you checked wether even the last stimulis have been processed, or did your simulation stop before that?

 

Have a nice simulation

  Eilert

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Contributor
Contributor
6,301 Views
Registered: ‎06-03-2011

Re: Accounting for Latency, how ?

 

Hello Eilert,

 

Thank you for responding,

 

You wrote "You also know the simulation period, set in the System Generator block" : I'm working with AccelDSP not in Simulink/System Generator, are there some correspondence ?

 

The same thing for "So, in the Simulink Simulation Parameters dialog, you find the Simulation stop time.",

 

I don't understand the relationship between Simulink/System Generator blocks and AccelDSP,

 

____

Regards

Sofiene

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Advisor eilert
Advisor
6,298 Views
Registered: ‎08-14-2007

Re: Accounting for Latency, how ?

Hi Sofienne,

I know that you are using Accel-DSP for designing your algorithms.

But what are you using for simulation?

And how did you do the HW-Cosimulation if not with Simulink (and sysgen)?

 

 (Accel-DSP came mostly bundled with Sysgen, so there is a tight relation between them.)

 

Have a nice weekend ;-)

  Eilert

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Contributor
Contributor
6,289 Views
Registered: ‎06-03-2011

Re: Accounting for Latency, how ?

Hello Eilert,

 

Thank you for responding,

 

When I perform a HW-cosim, I do just those steps:

 

Opening AccelSDP,

Creating or opening my project,

Choosing the HW-cosim simulation flow,

Choosing my target board,

Proceeding step-by-step the HW-cosim simulation flow until verifying the HW-cosim on the board,

 

All the cited steps are performed without opening Matlab/Simulink,

 

Eilert, I think that there is something that I don't understand, or that there some missed important step, thank you to clarify it to me more,

 

____

Regards

Sofiene

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Advisor eilert
Advisor
6,283 Views
Registered: ‎08-14-2007

Re: Accounting for Latency, how ?

Hi sofiene,

there's probably more something like a communications problem.

I just took a look at the AccelDSP documentation and are a bit baffled too.

 

They describe how to start some HW-Cosim (and that the board setup is like in System Generator) but nothing is mentioned about the used simulator or how the testbench looks like.

 

So my first question is: How do you write the testbench for your design? Is it written in Matlab code too?

In that case matlab must be loaded in the background to do the simulation, even if you don't notice it.

 

Another question?

How is a normal simulation done? Or are you doing this in Matlab without starting AccelDSP at all?

 

Have a nice simulation

  eilert

 

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Contributor
Contributor
6,281 Views
Registered: ‎06-03-2011

Re: Accounting for Latency, how ?

 

Hello Eilert,

 

Thank you for responding,

 

How do you write the testbench for your design? Is it written in Matlab code too? -> Yes, there is an implicit communication between Matlab (and not Simulink as it appear) and AccelDSP. At the launching of AccelDSP, a connection with Matlab is established (without an explicit opening of Matlab).

 

How is a normal simulation done? Or are you doing this in Matlab without starting AccelDSP at all? -> A normal HW-cosim is done just with AccelDSP and even without opening Matlab, it's done by following the cited steps.

 

____

Regards

Sofiene

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Advisor eilert
Advisor
6,276 Views
Registered: ‎08-14-2007

Re: Accounting for Latency, how ?

Hi Sofiene,

by "normal simulation" I mean without "HW-Co"

And still, how do you write your testbenches? In Matlab code?

 

----

 

My method of using system generator seems to be very similar to the AcelDSP method.

Of course I  have to use simulink to create a design model and also a HW-Cosim model.

But once that is doen everythig is controlled by matlab.

I create my stimuli in the workspace, start the simulink simulation with the sim command, which also works in the background. So I won't see anything happen during simulation.

And afterwards, the results are taken from the workspace again and been analyzed and plotted with matlab.

 

Maybe this kind of flow was one of the reasons to drop AccelDSP. Why support and maintain another gui, when everything can be done in Matlab/Simulink directly. And for using Mcode, there are Mcode blocks in the Xilinx blockset.

Also, when working in Matlab directly, one has control over all the settings that can be made. A higher degree of freedom.

 

Have a nice simulation

  Eilert

 

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Contributor
Contributor
3,237 Views
Registered: ‎06-03-2011

Re: Accounting for Latency, how ?

 

Hello Eilert,

 

Thank you for responding,

 

by "normal simulation" I mean without "HW-Co" -> It's done by the first step of the flow (in AccelDSP) named "Verify floating point", it's important to mention that the main input of AccelDSP is a M-File, so the results are the same obtained by running this M-File in Matlab,

 

And still, how do you write your testbenches? In Matlab code? -> Testbench is the HDL module that is generated (not synthesized) by the AccelDSP synthesis tool when the MATLAB design function is synthesized to an RTL model. When you execute the Verify RTL step in the AccelDSP flow, an HDL simulator runs a simulation on the Testbench which, in turn, applies stimulus to the inputs of the RTL model and compares the result to a known golden data.

 

And about working with AccelDSP, I have to do that, it's decided :)

 

____

Regards

Sofiene

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Advisor eilert
Advisor
3,230 Views
Registered: ‎08-14-2007

Re: Accounting for Latency, how ?

Hi Sofiene,

I don't want you to drop AcellDSP, just make you understand what may be the cause that this tool is no longer available.

 

However...

Since it is clear now that everything is done with the matlab language the tools behavior is similar to what I have seen with the original HDL-Coder toolbox from Matlab. (I've evaluated this toolbox some time ago and declined it)

 

The stimuli and results of your Matlab simulation are forwarded to your HDL- or HW-Cosimulation.

Since the tool knows how much latency has been introduced to your design during synthesis it is able to calculate wether you will see all of the simulation results within your formerly specified simulation time. If not, you get the message you observed, while still you may be able to see a lot of results. And depending on your design, this may be sufficient for you.

 

Wether you can overcome this message depends on your design.

Does it have signals like DataValid, Write or Read for controlling the data flow?

The simulation time basically depends on the ammount of input samples that you have defined.

When you can put the design in a state that causes no more internal events, and keep it there for the time of the latency then the tool might recognize this and stop giving this message.

 

Have a nice simulation

   Eilert

 

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Contributor
Contributor
3,224 Views
Registered: ‎06-03-2011

Re: Accounting for Latency, how ?

 

Hello Eilert,

 

Thank you for responding,

 

Since the tool knows how much latency has been introduced to your design during synthesis“ -> How to get it knowledge ? This is the real question,

 

When you can put the design in a state that causes no more internal events, and keep it there for the time of the latency” -> How? This is another important question,

 

About the M-code that I try to run it, it’s a very basic example, it’s a simple modulator. You find it attached,

 

And about this matter or this topic, I found this description in AccelDSP help:

 

Accounting for Latency in the Hardware Co-Sim Script File:

The Hardware Co-Sim Script File is a copy of the original MATLAB script file that compares the Floating Point Simulation Results with the Fixed Point Simulation Results. In the example shown below, the script file produces an error if the difference is more than 0.1%, a relative difference of “0.001”. If you are using the Hardware Co-Simulation flow, then you may want to use and modify this file after the first simulation run to add additional test vectors, since simulation speed is very fast. In the file shown below, this can be accomplished by changing “len” to be a value greater than “256”, e.g. “len = 1024;”

Under most conditions, you will not have to modify the Hardware Co-Sim Script File to adjust for hardware latency. However, if your design has a Latency whose value is greater than the Throughput, you MUST modify the script file to prevent the comparison of invalid-to-valid data. For example, suppose the design has Latency (Number of Startup Cycles) of 3, and a Throughput of 1. Within the hardware simulation, the first piece of valid output data will be on the third clock cycle. The first two cycles output invalid data. As such, the comparison between the Floating Point data and the Fixed Point (hardware) will be skewed. The first set of data from the Floating Point has to be compared against the third set of data from the hardware. Therefore, the comparison becomes the difference between “<golden_from_floating>(1:end-2) - <data_from_hardware>(3:end)”.

 

This description is followed by an example (the attached image). But I don’t understand it ! So if you can clarify it for me or summarize it,

 

I have to solve this problem as soon as possible

 

____

Regards

Sofiene

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