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Visitor rica.soles
Visitor
552 Views
Registered: ‎06-01-2018

DDS Compiler

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I need help with configurate the DDS compiler. I do my program in VHDL and i used de GUI for generate the core DDS. But i think it's wrong becouse when simulate not generate nothing. In sphase_td it must be see the value sin /cos in binary. Thanks you for your attention.

VirtualBox_ISE_14.7_VIRTUAL_APPLIANCE_10_12_2018_23_05_36.png

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Accepted Solutions
245 Views
Registered: ‎06-21-2017

Re: DDS Compiler

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In your test bench, you should add a couple lines like:

 sphase_tv  <= '1';
sphase_td  <= x"0015"; -- or whatever you want the phase increment to be.

 

Note that setting the phase increment to zero will give you a constant full scale value for a cosine and a constant zero for a sine value.

8 Replies
Moderator
Moderator
530 Views
Registered: ‎08-16-2018

Re: DDS Compiler

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Hi, 

Can you please share the design in zipped format. 

Please run the reset_project command before uploading it as shown in attached figure (it will clean all the Vivado-generated files).

 

 

Screenshot_3.jpg
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517 Views
Registered: ‎06-21-2017

Re: DDS Compiler

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I can't tell from your screenshot which signal is connected to which pin on the DDS, but if any of the input signals are undefined, the simulation will not produce a good result.  Also, does your test bench reset the DDS at start up?  It should.

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Moderator
Moderator
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Registered: ‎08-16-2018

Re: DDS Compiler

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Hi, 

Can you please upload the design on the forum. 

If size of the design is large, then you can use 'reset_project' command on tcl-console.

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Visitor rica.soles
Visitor
340 Views
Registered: ‎06-01-2018

Re: DDS Compiler

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I work with ISE DESING and my code is:

entity sdr1 is
        port(
                
                clk: in STD_LOGIC;
                sphase_tv: in STD_LOGIC;
                mdata_tv: out STD_LOGIC;
                sphase_td : in STD_LOGIC_VECTOR(15 downto 0):="0000000000000000";
                mdata_td : out STD_LOGIC_VECTOR (31 downto 0)
                
            );
end sdr1;

architecture Behavioral of sdr1 is
    signal CLK_6Mhz : STD_LOGIC;
    

--inicializa reloj

component reloj
port
 (-- Clock in ports
  CLK_IN1           : in     std_logic;
  --Clock out ports
  CLK_OUT1          : out    std_logic
 );
end component;

--inicializa el DDS

COMPONENT DDS
  PORT (
    aclk : IN STD_LOGIC;
    s_axis_phase_tvalid : IN STD_LOGIC;
    s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    m_axis_data_tvalid : OUT STD_LOGIC;
    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;

begin

reloj_inst : reloj
  port map
   (-- Clock in ports
    CLK_IN1 => clk,
    -- Clock out ports
    CLK_OUT1 => CLK_6Mhz
     );

    
seno : DDS
  PORT MAP (
    aclk => CLK_6Mhz,
    s_axis_phase_tvalid => sphase_tv,
    s_axis_phase_tdata  => sphase_td,
    m_axis_data_tvalid  => mdata_tv,
    m_axis_data_tdata   => mdata_td
  );

end Behavioral;

When I simulate it does not generate any value in the output m_axis_data_tdata.

Screenshot.png
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Visitor rica.soles
Visitor
339 Views
Registered: ‎06-01-2018

Re: DDS Compiler

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Thanks for you help but I work in ISE DESING is diferent software and aplicattion.

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322 Views
Registered: ‎06-21-2017

Re: DDS Compiler

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sphase_tv is undefined in your simulation.  You will not get a defined output unless all of the inputs to the DDS have a valid logic level.

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Visitor rica.soles
Visitor
307 Views
Registered: ‎06-01-2018

Re: DDS Compiler

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Any advice? or any example?

I would appreciate.

Thanks

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246 Views
Registered: ‎06-21-2017

Re: DDS Compiler

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In your test bench, you should add a couple lines like:

 sphase_tv  <= '1';
sphase_td  <= x"0015"; -- or whatever you want the phase increment to be.

 

Note that setting the phase increment to zero will give you a constant full scale value for a cosine and a constant zero for a sine value.