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Observer mferenc
Observer
7,048 Views
Registered: ‎04-03-2011

FIR filter problem on Spartan 3E

Hello!

 

I am using a Nexys 2 board (made by Digilent) with a Spartan3E 1200 FPGA in it with an AD and a DA converter to filter audio signals. The converters are on additional Digilent made boards (PmodAD1 and PmodDA2) - both have 12 bit resolution.

I tried to implement some FIR filters with coefficients generated with Matlab's FDATool and generated with the Xilinx FIR Compiler.

Digilent has provided some reference components written in VHDL for both the AD and the DA converters, however these are driving the mentioned circuits at very high frequencies - the ADC is driven at 12.5 MHz, which is, as I understood, the sampling frequency. It's worthless to say that is very hard to generate low-order FIR filters for audio frequency filtering at this sampling frequency (actually this 12.5 MHz frequency should be divided bu 16, as the ADC sends a 16 bit long "pack" serially for each and every sample). So I have tried to reduce the sampling frequency to only 50 MHz / 64 (that is 781.25 kHz - which translates into 48.828 kHz for every bit in the 16 bit "pack") hoping that this will help me design more simple filters. When I ran the FIR Compiler to generate the corresponding filter (I tried several band pass filters at 1, 2 and 4 kHz) and tried it out, nothing was functioning.  And by that I mean the in ALL cases the output of the DAC had exactly 5Vpp (whereas the input only had 0.5Vpp with 0.5V offset AND the reference voltage is 3.3V). Another probleam was that the filter didn't work as I expected but it generated some randomly changing rectangular wave with all-the-time-changing duty (mostly below 40%) - and this output was independent of the input, I have tried the signal generator with sinusoidal, rectangular and triangular waves too.

 

Does anyone have any idea what could cause this problem? I can attach the existing source code if needed.

 

Thank you in advance!

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6 Replies
Teacher rcingham
Teacher
6,988 Views
Registered: ‎09-09-2010

Re: FIR filter problem on Spartan 3E

My understanding was that the further the cut-off frequency was below the Nyquist frequency, the simpler (fewer poles) the filter.

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"If it don't work in simulation, it won't work on the board."
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Observer mferenc
Observer
6,984 Views
Registered: ‎04-03-2011

Re: FIR filter problem on Spartan 3E

Yes, this was my understanding too.

I think the problem is (at least one of them) that I'm using very short frequency intervals for the bandpass filters. For example if I want a bandpass filter with central frequency of 31.25Hz at a sampling frequency of 781.25kHz, fdatool generates a lowpass filter with cut-off frequency near 1kHz. I could somehow correct this problem with using a smaller sampling frequency, but the thing is just not working, the filter is not behaving as a filter, or the filter + the DAC is making trouble, I don't know which of these two.

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Teacher rcingham
Teacher
6,964 Views
Registered: ‎09-09-2010

Re: FIR filter problem on Spartan 3E

Do you really mean a central frequency of 31.25Hz? (not 31.25kHz)

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"If it don't work in simulation, it won't work on the board."
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Observer mferenc
Observer
6,957 Views
Registered: ‎04-03-2011

Re: FIR filter problem on Spartan 3E

That is correct. I'd like to implement ten band-pass filters with the following central frequencies: 31.25 Hz, 62.5 Hz, 125 Hz, 250 Hz, 500 Hz, 1 kHz, 2 kHz, 4 kHz, 8 kHz and 16 kHz. This is the reason why I have set a sampling frequency of 48.8 kHz instead of 781kHz.

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Teacher rcingham
Teacher
6,935 Views
Registered: ‎09-09-2010

Re: FIR filter problem on Spartan 3E

Those bottom filters have very high Q! No wonder the filter design tool is having problems generating something close.

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"If it don't work in simulation, it won't work on the board."
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Observer mferenc
Observer
6,927 Views
Registered: ‎04-03-2011

Re: FIR filter problem on Spartan 3E

Ok. So let's assume that I do not need those first four or five filters. I have implemented successfully the 1kHz and the 2 kHz band pass filters, but the 4 kHz is not working, nor are the 8 kHz and 16 kHz filters. And this is the point where I see no logic in the behavior of Xilinx's FIR Compiler. Why can it generate the 1 kHz and 2 kHz filters correctly, but not the others?

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