UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
2,226 Views
Registered: ‎04-20-2009

Pipeling My Design

I am trying to develop a fourth order fractional filter to meet speed. I want the design to run at 60 MHz but after I get my XST report the estimated clock speed is 24.8 MHz on my original design and when I manually insertpipe stage I can only improve the performance up to 39.2 MHz. But the is done manually. I am wondering is there a way I can have Accel DSP automatically pipeline my design through code so that the design can then meet  speed.
0 Kudos