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Registered: ‎12-10-2018

Xilinx FFT IP - Availability of bit-reversed order for the input


Currently the Xilinx FFT IP allows the use of natural order for both input and output, or natural order for input and bit-reversed order for output, but not bit-reversed order for input and natural order for output.

There is an answer record from 2015 stating that it is in the roadmap of the 2016 release, and there is a question about this in the forum from 2017 where a Xilinx employee mentionned that is is on the roadmap.

Is it possible to have an update on this ? Is it really planned to be implemented, and if yes when ?

This is an important feature, because if convolution or correlation wants to be computed by means of FFT, having bit-reversed order for both input and output allows a significant saving in memory and an appreciable reduction of the latency.