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FIR core and fixed point notation in the wizard

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Adventurer
Posts: 58
Registered: ‎03-16-2010
Accepted Solution

FIR core and fixed point notation in the wizard

[ Edited ]

When setting up a FIR core, it asks how many bits the input has and how many are fractional bits. The guides talk about this like FIX_15_8 and UFIX_8_8.

 

But suppose that I have signed 16-bit data which is supposed to be a value between -1 and 1. Does this mean the format would be FIX_16_16? Or FIX_15_15? Or even FIX_16_15?

 

I generated a FIR core using 16 bits input and told it I had 16 bits for the fractional value. Is this correct, or should this be 16 bit wide input with 15 bits fractional data (as the first bit is a sign bit)?


Accepted Solutions
Xilinx Employee
Xilinx Employee
Posts: 3,081
Registered: ‎11-28-2007

Re: FIR core and fixed point notation in the wizard

If the data is in the range of [-1, 1), use FIX_16_15. The fixed point data should be in the 2's complement format.

 


cyberwizzard wrote:

When setting up a FIR core, it asks how many bits the input has and how many are fractional bits. The guides talk about this like FIX_15_8 and UFIX_8_8.

 

But suppose that I have signed 16-bit data which is supposed to be a value between -1 and 1. Does this mean the format would be FIX_16_16? Or FIX_15_15? Or even FIX_16_15?

 

I generated a FIR core using 16 bits input and told it I had 16 bits for the fractional value. Is this correct, or should this be 16 bit wide input with 15 bits fractional data (as the first bit is a sign bit)?




Cheers,
Jim

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All Replies
Xilinx Employee
Xilinx Employee
Posts: 3,081
Registered: ‎11-28-2007

Re: FIR core and fixed point notation in the wizard

If the data is in the range of [-1, 1), use FIX_16_15. The fixed point data should be in the 2's complement format.

 


cyberwizzard wrote:

When setting up a FIR core, it asks how many bits the input has and how many are fractional bits. The guides talk about this like FIX_15_8 and UFIX_8_8.

 

But suppose that I have signed 16-bit data which is supposed to be a value between -1 and 1. Does this mean the format would be FIX_16_16? Or FIX_15_15? Or even FIX_16_15?

 

I generated a FIR core using 16 bits input and told it I had 16 bits for the fractional value. Is this correct, or should this be 16 bit wide input with 15 bits fractional data (as the first bit is a sign bit)?




Cheers,
Jim
Adventurer
Posts: 58
Registered: ‎03-16-2010

Re: FIR core and fixed point notation in the wizard

[ Edited ]

Thanks for the clarification.

 

Since the result is 2's complement (like the input), am I correct in assuming the result (without integer components, which should be zero) can be reassembled into signed 16-bit (FIX_16_15) by using the first bit for the sign, followed by the first 15 bits of the fractional part?

If so, I am wondering why I get a DC offset from the filters...

Xilinx Employee
Xilinx Employee
Posts: 3,081
Registered: ‎11-28-2007

Re: FIR core and fixed point notation in the wizard

The output is in 2's complement as well. There is no need to reassemble.

 


cyberwizzard wrote:

Thanks for the clarification.

 

Since the result is 2's complement (like the input), am I correct in assuming the result (without integer components, which should be zero) can be reassembled into signed 16-bit (FIX_16_15) by using the first bit for the sign, followed by the first 15 bits of the fractional part?

If so, I am wondering why I get a DC offset from the filters...




Cheers,
Jim
Adventurer
Posts: 58
Registered: ‎03-16-2010

Re: FIR core and fixed point notation in the wizard

Perhaps I used the wrong wording.

 

My input is FIX_16_15 and since the filter coefficients should prevent an integer result, I want a FIX_16_15 result from the FIR filter.

 

Since the output is something like FIX_58_48 due to bit growth, I was planning on using the first bit and the first 15 fractional bits to create a FIX_16_15 result again (similar to the input). But since I'm not getting the expected results I was wondering if that idea was wrong.

 

On the other hand, if I could force the FIR generator to create FIX_16_15 output in the first place that would suffice as well.