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No macro available for ADD/SUB/MULT DSP instantiation on US/US+?

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Visitor
Posts: 6
Registered: ‎08-11-2017

No macro available for ADD/SUB/MULT DSP instantiation on US/US+?

I am trying to migrate some LPM_ADD_SUB and LPM_MULT (Altera) instantiations to the equivalent macros on Vivado for US and US+, but after reading the Language Template section and the Design Flow for Intel FPGA (UG1192), nothing equivalent has been found.

 

In the Language Template, I have found some MULT and ADD_SUB macros, but apparently they are not available for US or US+. I have also tried to infer the multiplication, but the internal pipelining of the DSP48E2 is not well done. It is capable of activating some input pipes, but not the fully piped for maximum timing performance.

 

The Design Flow suggests to check the IP catalog to replace the LPM MegaFunctions. For instance, there is a Multiplier IP on the catalog. The problem being, as my previous code is highly variable in input/output/pipe parameters, I would have to generate several Multipliers IPs for my design.  

 

My best bet would be to construct a wrapper around the Multiplier IP to manipulate the parameters regarding input and output width as well as pipelining or there is an easier solution? Perhaps, I am missing something.

Voyager
Posts: 1,636
Registered: ‎06-24-2013

Re: No macro available for ADD/SUB/MULT DSP instantiation on US/US+?

Hey @gstorto,

 

... nothing equivalent has been found.

As far as I can tell, the Megafunctions are equivalent to Xilinx IP cores, although they might be more flexible. 

 

I have also tried to infer the multiplication, but the internal pipelining of the DSP48E2 is not well done.

It is capable of activating some input pipes, but not the fully piped for maximum timing performance.

I'd like to disagree here, unless you want to use special DSP tricks, the inference results should be as good as it gets. Do you have an example where proper inference fails and doesn't provide the expected result?

 

I would have to generate several Multipliers IPs for my design.

You could also generate them based on the requirements or automatically in advance. After all you have a very felxible scripting language (TCL) at your disposal.

 

My best bet would be to construct a wrapper around the Multiplier IP to manipulate the parameters regarding input and output width as well as pipelining or there is an easier solution?

That would definitely work as well, although it might not be worth the effort.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
Visitor
Posts: 6
Registered: ‎08-11-2017

Re: No macro available for ADD/SUB/MULT DSP instantiation on US/US+?

Hi @hpoetzl,

 

The project I have used to run the statistics is attached. These are the results I have gotten:

 

Fclk = 350MHz
------------------------------
mult_ip,pipe=3,wns=-200ps mult_ip,pipe=4,wns=+307ps mult_ip,pipe=5,wns=+640ps mult_ip,pipe=6,wns=+1026ps mult_ip,pipe=7,wns=+1481ps ------------------------------ inference,pipe=3,wns=-249ps inference,pipe=4,wns=-72ps inference,pipe=5,wns=+806ps inference,pipe=6,wns=+749ps inference,pipe=7,wns=+1481ps

If you want to repeat the tests, adjust the generics MODE and LATENCY of the tmp_dsp_test.vhd file accordingly and launch:

 

vivado -mode batch -source launch.tcl

It seems to me that the Multiplier IP is much more reliable, even though the inferred code got a better WNS at pipe=5. I was indeed wrong saying that the inferred code could not fully pipeline the DSP48E2 instances, but it is not optimal for most pipe configurations.

 

PS: I am running Vivado 2017.1, so you may run into problems if you are using another version.

 

Teacher
Posts: 5,143
Registered: ‎03-31-2012

Re: No macro available for ADD/SUB/MULT DSP instantiation on US/US+?

@gstorto have you seen the MULT_MACRO.v and ADDSUB_MACRO.v files in Xilinx\Vivado\201x.x\data\verilog\src\unimacro directory?

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Visitor
Posts: 6
Registered: ‎08-11-2017

Re: No macro available for ADD/SUB/MULT DSP instantiation on US/US+?

Hello @muzaffer,

 

Yes, I had seen these macros on Language Template (Vivado). They are not quite convenient to me as they are not available for US/US+ and are limited to one DSP48 instantiation. The LPM (Altera) I am trying to replace works like the Multiplier IP, but can be instantiated as a macro.

 

Would you know if there is a way to forward the LATENCY and WIDTH parameters as entity generics from the IP generated file (attached)? In this manner, I could instantiate the IP the same way I did with LPM macros.

 

I tried to dumbly copy the hdl/* and synth/* files from the Multiplier IP .xcix, modify the attached file to forward the desired generics and try to synthesize them all using read_vhdl + synth_design, but I get an error in the encrypted envelope during synthesis. I don't think they are meant to be synthesized without a synth_ip command, am I right?