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Visitor
Visitor
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Registered: ‎04-04-2018

128b AXI device

Hi,

 

I created a peripheral with 128b registers with 'Create and Package new IP...' and then manually changing C_S_AXI_DATA_WIDTH to 128. When I do that I see that the ADDR_LSB variable is not computed correctly. Here is a snippet of generated code:

 

    //local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
    //ADDR_LSB is used for addressing 32/64 bit registers/memories
    //ADDR_LSB = 2 for 32 bits (n downto 2)
    //ADDR_LSB = 3 for 42 bits (n downto 3)

    localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32)+ 1;

 

For C_S_AXI_DATA_WIDTH == 128 it should compute ADDR_LSB = 4 instead of 5 which is computed with the expression above. Instead of computing the value as shown above it should be:

 

   localparam integer ADDR_LSB = log2(C_S_AXI_DATA_WIDTH / 8);

 

Right?

 

Regards,

Jan

1 Reply
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Moderator
Moderator
579 Views
Registered: ‎11-09-2015

Re: 128b AXI device

Hi @jan.h,

 

I think you are right. It seems that it has been written only for 32/64 bits not others register width.

 

If you check the VHDL code, there is this comment:

-- Example-specific design signals

 

It seems to say that it has been written on for this example, thus you should modify it.

 

However it would be better with a more adaptive way so I will report it to development.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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