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Explorer
Explorer
10,076 Views
Registered: ‎10-19-2012

7 Series MIG ILA and VIO cores not generated ?

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Hi all, I want to debug my customized MIG core using ChipScope (DDR3). I have enabled debug generation in the IP GUI, but it only generates the needed VHDL code and instances of both the ILA and the VIO, but no synthesizable/implementable cores. Does this mean that this ILA and VIO cores need to be generated separately ? (in which case why does the GUI ask for a buffer depth). I noticed that it also "marked for debug" various signals, enabling me to generate the ILA core with the "Set up Debug" Vivado Feature, but I don't want to do this, I want to use the instances of the cores and connect them in the HDL.

 

I'm using Vivado 2013.4.

 

Another thing, does a current licence for ChipScope work for Vivado Logic Analyzer ?

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Xilinx Employee
Xilinx Employee
15,438 Views
Registered: ‎07-11-2011

Re: 7 Series MIG ILA and VIO cores not generated ?

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Hi,

 

After genarting the core, if you right clock on .xci and genarte example deisgn all the cores will be genarted and you should be able to see them in hierarchy, can you confirm if you do not see this in example design as well?

 

Edit

MIG_ILA.png

 

The depth in GUI refers to the same cores and the list of signals will be given in hardware debug guide

http://www.xilinx.com/support/answers/43879.html

 

The ILA cores that come with example deisgn are mainly for Calibration failure issues.

If your custom board calibrates successfully and wanted to analyze other signals you may generate the ILAs and add them to RTL

 

If you are using VSystem edition I think Chipscope is free for other licenses please share your license file so that one of us will look at it and comment, else you may check the chipscope license feature in License Manager as well

 

Hope this helps

 

Regards,

Vanitha

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5 Replies
Xilinx Employee
Xilinx Employee
10,070 Views
Registered: ‎10-24-2013

Re: 7 Series MIG ILA and VIO cores not generated ?

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Hi,
Please check the insert flow @ http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug936-vivado-tutorial-programming-debugging.pdf
Thanks,Vijay
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Xilinx Employee
Xilinx Employee
15,439 Views
Registered: ‎07-11-2011

Re: 7 Series MIG ILA and VIO cores not generated ?

Jump to solution

Hi,

 

After genarting the core, if you right clock on .xci and genarte example deisgn all the cores will be genarted and you should be able to see them in hierarchy, can you confirm if you do not see this in example design as well?

 

Edit

MIG_ILA.png

 

The depth in GUI refers to the same cores and the list of signals will be given in hardware debug guide

http://www.xilinx.com/support/answers/43879.html

 

The ILA cores that come with example deisgn are mainly for Calibration failure issues.

If your custom board calibrates successfully and wanted to analyze other signals you may generate the ILAs and add them to RTL

 

If you are using VSystem edition I think Chipscope is free for other licenses please share your license file so that one of us will look at it and comment, else you may check the chipscope license feature in License Manager as well

 

Hope this helps

 

Regards,

Vanitha

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
Visitor maxbaker
Visitor
9,249 Views
Registered: ‎02-06-2014

Re: 7 Series MIG ILA and VIO cores not generated ?

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Hi,

 

Is there a way to re-generate the .xci's for the VIO and ILA on the example design from the command line?

 

I'm trying to automate the integration of MIG into our flow, with the option to add or remove the debug portion.

 

Thanks,

-m

 

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Scholar dwisehart
Scholar
9,247 Views
Registered: ‎06-23-2013

Re: 7 Series MIG ILA and VIO cores not generated ?

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For ILA take a look at this thread:http://forums.xilinx.com/t5/Implementation/Is-it-possible-to-disable-ILA-not-delete-in-Vivado/m-p/472166#M9419

 

All of the commands I put in the XDC file can be put straight into the command line.  Or you can create the separate XDC file for the ILA probes as I did, and enable and disable that file from the command line.  Your choice.

 

VIO is a little different in that it has to be synthesized in, but assuming you have the VIO IP already in your design, you can enable and disable it in the same way.

 

Regards,

Daniel

 

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Visitor maxbaker
Visitor
9,245 Views
Registered: ‎02-06-2014

Re: 7 Series MIG ILA and VIO cores not generated ?

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Excellent, thanks Daniel, I'll have a look.
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