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Registered: ‎02-08-2017

AXI DataMover v5.1 Data Realignment Engine (DRE) with 8-bit Stream Data Width?

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Hello,

 

I am working on an FPGA (really PL in Zynq7000) application that contains several logic blocks in the design that write/read using different data widths (8, 16, 32, 64) to/from PL-connected DDR3 memory.  Each of these logic blocks employs an AXI DataMover v5.1 IP core, where the stream data width varies, but the memory map data width is set to 512 bits in each instance for increased DDR3 bandwidth.

 

One of my logical units needs to periodically read a variable number of bytes from the memory, so only MM2S is enabled and the stream data width is set to 8 bits with the memory map data width set to 512 bits (64 bytes).  In this configuration, it is highly likely (63 out of 64 possible values) that the requested byte address from the memory (SADDR in the CMD word) is not aligned to the 512-bit/64-byte boundary.  The documentation for the core (pg022 version 5.1 11/18/15, pg. 7) states the following with regards to unaligned transfers:

 

pg022_unaligned_transfers.PNG

 

Therefore, this appears to be a prime example of when the Data Realignment Engine or DRE should be enabled in the core.  I glossed over this when I first used the core because I felt it was an advanced feature that I wouldn't need for my simple application, but I've since revisited it when I was having some periodic data corruption at the end of my read transfers.

 

So, I enabled DRE by checking the "Allow Unaligned Transfer" checkbox in the Advanced page of the GUI.  I also set the DRR bit of the CMD word to '1' when the lower 6-bits (64 bytes) of the SADDR are not '0'.  Lastly, I set the DSA register to "000000" to indicate that byte-lane 0 was my reference byte for the stream interface (in fact, I only have one byte).  Unfortunately, I still see the same corrupt data at the end of some of my reads.

 

So I started investigating what the core was doing under the hood with my GUI settings, which is possible since the source files for the IP are available in the IP hierarchy (thank you!).  I saw that the pertinent generic values were being set correctly when the core was instantiated.  Then I burrowed down to find the most relevant source file for my use case, which is the axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd file.  

 

This entity has the following constant declaration to determine whether DRE is actually included in the core:

 

Constant INCLUDE_DRE : integer range  0 to    1 := func_include_dre(C_INCLUDE_MM2S_DRE,
                                                                    C_MM2S_SDATA_WIDTH);

 

In my case, C_INCLUDE_MM2S_DRE = 1 and C_MM2S_SDATA_WIDTH = 8.

 

The func_include_dre function is written as follows:

 

    -------------------------------------------------------------------
    -- Function
    --
    -- Function Name: func_include_dre
    --
    -- Function Description:
    -- This function desides if conditions are right for allowing DRE 
    -- inclusion.
    --
    -------------------------------------------------------------------
    function func_include_dre (need_dre          : integer;
                               needed_data_width : integer) return integer is
      Variable include_dre : Integer := 0;    
    begin    
      If (need_dre = 1 and 
          needed_data_width < 128 and
          needed_data_width >   8) Then
         include_dre := 1;      
      Else 
        include_dre := 0;
      End if;
      Return (include_dre);
    end function func_include_dre;

 

So now I'm really confused by the inclusion of the needed_data_width > 8 condition, which means DRE is not being included for my core.  The documentation clearly says that a transfer is considered aligned or unaligned based on the memory map data width and that DRE is supported for stream data widths up to 64 bits.  If this is true, then why is DRE not included when the stream data width is 8 bits?  Does this mean it isn't actually needed?  If so, then I clearly don't understand the purpose of the DRE and could benefit from an explanation.

 

Thanks,

 

Scott

 

P.S. I'm currently locked into using Vivado 2015.2 for the project, but the AXI DataMover core has not been upgraded since version 5.1, which is available in this Vivado release.

 

 

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Visitor
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Registered: ‎02-08-2017

I haven't solved my issues yet, but I think I've convinced myself that the Xilinx documentation as it relates to DRE is contradictory.

 

Here is an excerpt from the very latest AXI DMA Product Guide (LogiCORE IP AXI DMA 7.1 PG021 October 5, 2016, page 73) with regards to alignment:

 

dre_pg021.png

So the first highlighted section says that the stream data width defines alignment.  The second highlighted section says that the memory map data width defines alignment.  The AXI DataMover documentation itself says the memory map data width defines alignment, yet the IP source doesn't include DRE when the stream data width is 8-bit, which would indicate that the stream data width really defines alignment.

 

 

I don't have official confirmation, but based on my investigations it appears that only the stream data width matters.  I always issue reads/writes on stream data width aligned boundaries, so I don't think DRE is doing anything useful in my application.

 

Scott

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Visitor
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Registered: ‎02-08-2017

I haven't solved my issues yet, but I think I've convinced myself that the Xilinx documentation as it relates to DRE is contradictory.

 

Here is an excerpt from the very latest AXI DMA Product Guide (LogiCORE IP AXI DMA 7.1 PG021 October 5, 2016, page 73) with regards to alignment:

 

dre_pg021.png

So the first highlighted section says that the stream data width defines alignment.  The second highlighted section says that the memory map data width defines alignment.  The AXI DataMover documentation itself says the memory map data width defines alignment, yet the IP source doesn't include DRE when the stream data width is 8-bit, which would indicate that the stream data width really defines alignment.

 

 

I don't have official confirmation, but based on my investigations it appears that only the stream data width matters.  I always issue reads/writes on stream data width aligned boundaries, so I don't think DRE is doing anything useful in my application.

 

Scott

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