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Scholar beandigital
Scholar
3,810 Views
Registered: ‎04-27-2010

AXI interconnect width mismatch

I have a Vivado BD and I am getting a few errors like the one shown below

 

[BD 41-235] Width mismatch when connecting pin: '/axi_interconnect_0/m00_couplers/auto_pc/m_axi_rid'(1) to net 'auto_pc_to_m00_couplers_RID'(6) - Only lower order bits will be connected.

 

Can I ignore these?

Thanks

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1 Reply
Xilinx Employee
Xilinx Employee
3,804 Views
Registered: ‎08-01-2008

Re: AXI interconnect width mismatch

Check below link

http://forums.xilinx.com/t5/Embedded-Development-Tools/AXI-ID-Widths-BD-41-235/td-p/531385
Thanks and Regards
Balkrishan
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