06-01-2019 08:35 PM
I'm trying to add an edif netlist in my project. I am following the methodology described in AR# 54074:
write_verilog -mode synth_stub module_stub.v
Add both module.edf and module_stub.v to the project.
If I use Add Sources with only module_stub.v then Add Module works (I can add a black-box module in my project).
But if I use Add Sources with module.edf and module_stub.v (as written in the AR above) then the Add Module window is empty (cannot add module in my project).
Could you please explain what I am doing wrong?
06-02-2019 10:31 PM
By saying "the Add Module window is empty", do you mean you could not select the two files when you perform Add Sources operation? Can you illustrate the problem?
06-03-2019 08:45 AM
Yes the Add Module window doesn't show the 2 files (module.edf and module_stub.v) when they are both added as sources.
But when I disable "Hide incompatible modules", I can see them grayed out with the following error message:
Failed to uniquely resolve reference. Multiple different modules were found that match the name 'module'.
06-03-2019 05:00 PM
What Vivado release are you using? Would you please attach the two files so that I can try to reproduce the issue?
06-03-2019 07:49 PM
I am using 2018.2.
Cannot give you the files. They come from 3rd party IP vendor so they are confidential.
What I see is that there is a module name conflict between module.edf and module_stub.v.
This is at the top of the module.edf file:
(edifversion 2 0 0)
(keywordmap (keywordlevel 0))
This is the module_stub.v file:
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module module_name (
06-14-2019 01:37 PM
06-16-2019 07:20 PM
I can see both files in Add Sources window. They also display in Sources window after being added.
What's the specific problem at your end?
06-17-2019 06:57 AM
The problem occcurs when adding the module in the block design with the command Add Module.
The Add Module window is emply but these 2 files show up as incompatible modules.
06-17-2019 06:28 PM
OK, so you're talking about a different flow of adding RTL module to block design. Below is referenced from UG994.
The Add Module dialog box also provides a Hide incompatible modules check box that is enabled by default. This hides module definitions in the loaded source files that do not meet the requirements of the Module Reference feature and, consequently, cannot be added to the block design.
You can uncheck this check box to display all RTL modules defined in the loaded source files, but you will not be able to add all modules to the block design. Examples of modules that you might see when deselecting this option include:
° Files that have syntactical errors
° Modules with missing sources
° Module definitions that contain or refer to an EDIF netlist, a DCP file, another block design, or unsupported IP
It looks adding wrapper that refers to a netlist is not supported.