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Explorer
Explorer
8,903 Views
Registered: ‎09-08-2014

Adding a VDMA to a design

I have a design running on the Zedboard. It is based on the FMC- IMAGEON Vita Pass through tutorial. I have taken this design and modified it. I want to further modify it by adding a VDMA so that I can cope with different resolutions and frame rates.I am following the design guide lines in the LogiCORE IP Video In to AXI4-Stream v3.0 and the AXI Video Direct Memory Access v6.1. I have added the VDMA to the design and I get the following errors:

 

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /processing_system7_0_axi_periph/s01_couplers/auto_pc/S_AXI(100000000) and /axi_vdma_0/M_AXI_MM2S(142857132)


ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /processing_system7_0_axi_periph/s01_couplers/auto_pc/S_AXI(zed_hdmi_processing_system7_0_0_FCLK_CLK0) and /axi_vdma_0/M_AXI_MM2S(zed_hdmi_processing_system7_0_0_FCLK_CLK1)


CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(3) and /axi_vdma_0/M_AXIS_MM2S(4)

 

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_vdma_0/S_AXIS_S2MM(100000000) and /fmc_imageon_vita_color/v_cfa_0/video_out(142857132)


ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axi_vdma_0/S_AXIS_S2MM(zed_hdmi_processing_system7_0_0_FCLK_CLK0) and /fmc_imageon_vita_color/v_cfa_0/video_out(zed_hdmi_processing_system7_0_0_FCLK_CLK1)

 

Are there any good examples that will show me how to connect up the VDMA?

 

 

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Xilinx Employee
Xilinx Employee
8,894 Views
Registered: ‎02-06-2013

Hi

 

Check below links

 

http://www.xilinx.com/support/documentation/application_notes/xapp742-axi-vdma-reference-design.pdf

 

http://www.xilinx.com/support/documentation/application_notes/xapp741-high-performance-video-AXI-interconnect.pdf

Regards,

Satish

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Explorer
Explorer
8,880 Views
Registered: ‎09-08-2014

Where do I find out what to do with the following signals:

 

m_axi_mm2s_aclk

m_axis_mm2s_aclk

m_axi_s2mm_aclk

s_axis_s2mm_aclk

 

I understand from the LogicCORE IP AXI Video Direct Memory Access v6.1 product guide for Vivado design suite:

 

 AXI VDMA provides two clocking modes of operation: asynchronous and synchronous. In
async mode VDMA control, MM2S and S2MM Primary datapaths can all run asynchronously
from each other. Checking Enable Asynchronous Mode in the Vivado IDE enables this mode
and creates five clock domains.


• AXI4-Lite clock domain clocked by s_axi_lite_aclk
• mm2s clock domain on Memory Map side clocked by m_axi_mm2s_aclk
• s2mm clock domain on Memory Map side clocked by m_axi_s2mm_aclk
• s2mm clock domain on streaming side clocked by s_axis_s2mm_aclk
• mm2s clock domain on streaming side clocked by m_axis_mm2s_aclk


In asynchronous mode, the frequency of s_axi_lite_aclk <= m_axi_mm2s_aclk or
m_axi_s2mm_aclk.


Note: Make sure Memory Map side clock is equal to or greater than Streaming side clock to achieve
required performance.


In synchronous mode, all logic runs in a single clock domain. The signals
s_axi_lite_aclk, m_axi_mm2s_aclk, m_axi_s2mm_aclk, m_axis_mm2s_aclk, and
s_axis_s2mm_aclk must be tied to the same source otherwise undefined results occur.

 

The Enable Asynchronous Mode (Auto) tick block is ticked and is also grayed out. So it seems I've have no option other than to use Asynchronous mode. If this is the case then s_axi_lite_aclk <= m_axi_mm2s_aclk or m_axi_s2mm_aclk.

 

If I do this I get the following errors:

 

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /IPS/fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(3) and /IPS/axi_vdma_0/M_AXIS_MM2S(4)
INFO: [BD 41-237] Bus Interface property HAS_TKEEP does not match between

/IPS/fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(0) and /IPS/axi_vdma_0/M_AXIS_MM2S(1)


ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /IPS/fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(142857132) and /IPS/axi_vdma_0/M_AXIS_MM2S(100000000)

 

ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /IPS/fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(zed_hdmi_processing_system7_0_0_FCLK_CLK1) and /IPS/axi_vdma_0/M_AXIS_MM2S(zed_hdmi_processing_system7_0_0_FCLK_CLK0)
INFO: [BD 41-237] Bus Interface property HAS_TKEEP does not match between /IPS/axi_vdma_0/S_AXIS_S2MM(1) and /IPS/fmc_imageon_vita_color/v_cfa_0/video_out(0)

 

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /IPS/axi_vdma_0/S_AXIS_S2MM(100000000) and /IPS/fmc_imageon_vita_color/v_cfa_0/video_out(142857132)

 

ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /IPS/axi_vdma_0/S_AXIS_S2MM(zed_hdmi_processing_system7_0_0_FCLK_CLK0) and /IPS/fmc_imageon_vita_color/v_cfa_0/video_out(zed_hdmi_processing_system7_0_0_FCLK_CLK1)
validate_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1796.086 ; gain = 0.000

 

ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.

 

Any ideas?

 

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Explorer
Explorer
8,877 Views
Registered: ‎09-08-2014

not sure if this is progress but I've connected them all to the same clk and now I get:

 

CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /IPS/fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(3) and /IPS/axi_vdma_0/M_AXIS_MM2S(4)
INFO: [BD 41-237] Bus Interface property HAS_TKEEP does not match between /IPS/fmc_imageon_hdmio_rgb/v_rgb2ycrcb_0/video_in(0) and /IPS/axi_vdma_0/M_AXIS_MM2S(1)
INFO: [BD 41-237] Bus Interface property HAS_TKEEP does not match between /IPS/axi_vdma_0/S_AXIS_S2MM(1) and /IPS/fmc_imageon_vita_color/v_cfa_0/video_out(0)
validate_bd_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1897.695 ; gain = 0.000
success

 

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Explorer
Explorer
8,868 Views
Registered: ‎09-08-2014

To fix this I had to add a axis_subset_converter. I then had to change the master interface signal properties from 4 to 3 bytes (after changing it from auto mode to maual).

 

I could still do with some design guide lines as I've only validated the design.

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