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Visitor a.lisitsyn
Visitor
12,313 Views
Registered: ‎05-15-2015

Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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Hello!

 

I am new to a Vivado dcp concept and have some (maybe simple) question.

 

How can I add dcp (or netlist) of an IP to my own custom IP to speed up synthesis and generation of my IP?

 

For now, I have several ILAs in my own IP, that are added as .xci files to "Verilog synthesis" folder in "Package IP" wizard. However, when I add custom IP to a block design and start to generate block design it advanced very slowly, because it sequentially generates all ILAs from .xci files. Removing ILAs from custom IP incredibly speed up block design generation process. Another problem is that any modification in custom IP hdl sources (ILAs remains unmodified) makes Vivado regenerate custom IP core completely.

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Xilinx Employee
Xilinx Employee
22,014 Views
Registered: ‎09-20-2012

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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Hi,

 

Open the checkpoint using File-->open checkpoint command and run the write_edif command from the tcl console.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
12,306 Views
Registered: ‎08-01-2008

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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IP Packager does not accept DCP files as a source for a custom IP.

In Vivado 2013.3 and later an Error will be issued if a DCP is given as a source to the IP Packager.
Thanks and Regards
Balkrishan
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Visitor a.lisitsyn
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12,304 Views
Registered: ‎05-15-2015

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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Any workaround for speeding up?
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Xilinx Employee
Xilinx Employee
12,290 Views
Registered: ‎09-20-2012

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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Hi,

 

In vivado 2015.1 we have option "IP Cache", see if this helps.

 

Refer to page-25 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug896-vivado-ip.pdf for more details.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Xilinx Employee
Xilinx Employee
12,282 Views
Registered: ‎07-09-2013

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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You can add an edif and associated constraints files instead of the DCP.  When adding xdc files with the edif, be sure to set the scope to cell and scope to ref properties appropriately to get the xdc to apply to the edif module.

 

While a DCP is definately more convenent, the vivado frontend is a bit limited with nesting DCPs.  Packager stops you from adding since the reset of the system wouldn't work with it.

Visitor a.lisitsyn
Visitor
12,272 Views
Registered: ‎05-15-2015

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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How can I convert dcp files that I get by OOC compile to edif files? I tried read_checkpoint your_design.dcp
write_edif -force your_design.edn but it does not work.
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Xilinx Employee
Xilinx Employee
22,015 Views
Registered: ‎09-20-2012

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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Hi,

 

Open the checkpoint using File-->open checkpoint command and run the write_edif command from the tcl console.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Visitor a.lisitsyn
Visitor
12,259 Views
Registered: ‎05-15-2015

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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Thank you, it works. But can I automate it by some sort of tcl script?
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Visitor sgustafsson
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2,810 Views
Registered: ‎07-30-2014

Re: Adding xilinx IP dcp files for packaging custom IP to speed up synthesis

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IP packager (Vivado 2017.4) seems to accept DCP files as sub blocks when packaging IP. Adding a sub block in the dcp format becomes part of the hierarchy.  However, the module becomes a black box in implementation. Adding the DCP file to the project does not make a difference. Reopening the ip packager shows that dcp file is no longer in the project. Is there any way to make implementation use the DCP? 

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